Buried Layer Carrier Distribution in Semiconductor Devices
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Solution Overview
Problem
In non-epitaxial semiconductor processes, deep high-voltage wells formed by thermal diffusion lead to uneven carrier concentration, increasing turn-on resistance and the risk of carriers being driven into the field oxide layer, affecting the reliability of ultra-high-voltage semiconductor devices.
Innovation Solution
A buried layer with the same conductivity type as the semiconductor substrate is introduced under the deep high-voltage well region, distributing carrier concentration from the top surface to the bottom and reducing the concentration at the surface, thereby decreasing the turn-on resistance and preventing carrier accumulation in the field oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal diffusion and drive in (D/I) are used to form deep high-voltage wells, then the carrier concentration can be increased to achieve fully depleted state, but the carrier concentration will be distributed unevenly with high-concentration carriers concentrated at the top surface, increasing turn-on resistance
Solution Approach 1:
The patent segments the carrier concentration distribution by introducing a buried layer at a specific depth (5-15 μm) beneath the surface. This creates two distinct regions: a lower-concentration top layer (0-5 μm) and a higher-concentration buried layer (5-15 μm), which together achieve uniform overall distribution while enabling fully depleted state without excessive surface concentration that would increase turn-on resistance.
Solution Approach 2:
The patent transitions from a single-surface doping approach to a multi-depth doping strategy by introducing a buried layer at 5-15 μm depth. This vertical dimensionality change allows carrier concentration to be distributed throughout the drift region depth, achieving uniform distribution and fully depleted state while controlling surface concentration to maintain low turn-on resistance.
2Reliability
If carrier concentration of the top layer in the deep high-voltage well is increased to evenly distribute carrier concentration, then fully depleted state can be achieved, but the turn-on resistance of the ultra-high-voltage elements will be increased
Solution Approach 1:
The patent segments the doping profile into two distinct layers: a top layer (0-5 μm) with lower carrier concentration to maintain low turn-on resistance, and a buried layer (5-15 μm) with higher carrier concentration to achieve fully depleted state. This segmentation allows the device to achieve high voltage blocking capability without excessive turn-on resistance.
Solution Approach 2:
The patent applies local quality by creating different carrier concentrations at different depths: the top region (0-5 μm) has lower concentration to reduce turn-on resistance, while the buried region (5-15 μm) has higher concentration to achieve fully depleted state. Each region is optimized for its specific function, resolving the contradiction between turn-on resistance and fully depleted state achievement.
3Quantity of substance
If carriers of the deep high-voltage well are concentrated in the top portion, then the carrier concentration can be increased, but the carriers may easily be driven into the field oxide layer because of the high electric field, affecting the reliability of the elements
Solution Approach 1:
The patent segments the carrier distribution vertically by introducing a buried layer at 5-15 μm depth. This prevents excessive carrier concentration at the top surface (0-5 μm), reducing the electric field strength at the surface and minimizing the risk of carriers being driven into the field oxide layer, thereby improving element reliability while maintaining sufficient overall carrier concentration.
Solution Approach 2:
The patent redistributes carriers from a surface-concentrated single-dimension profile to a depth-distributed multi-dimension profile by introducing the buried layer at 5-15 μm. This vertical redistribution reduces surface carrier concentration and electric field strength, preventing carrier injection into the field oxide layer and improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates a fully depleted state in semiconductor devices, enhances reliability by reducing surface field and carrier concentration at the top surface, and decreases the probability of carriers being driven into the field oxide layer, resulting in improved breakdown voltage and reduced turn-on resistance.
Implementation Method 1
the deep high-voltage wells are formed by thermal diffusion and drive in (D/I), which will cause the carrier concentration to be distributed unevenly
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.