Buried Layer Photodetector for CMOS Integration
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Solution Overview
Problem
Conventional methods for creating photodiodes either limit CMOS integration and multipixel designs due to thick vertical regions or sacrifice Photon Detection Efficiency (PDE) by not allowing thick vertical regions, making them inefficient for detecting longer wavelengths.
Innovation Solution
The use of an epitaxial growth and buried layer process, which includes a substrate layer, buried layer, intrinsic layer, plug layer, p-plus layer, n-plus layer, and pre-metal dielectric layer, with trenches and an n-type epitaxial layer, enables efficient photon detection by allowing a thicker intrinsic region and better CMOS compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical process with top and bottom contact is used to create a thick vertical region, then Photon Detection Efficiency (PDE) is improved, but CMOS integration and multipixel designs are not allowed
Solution Approach 1:
The photodetector structure is segmented into distinct functional layers: a substrate layer for mechanical support, a buried layer for electrical connection, an intrinsic layer for photon absorption, and contact layers for electrical terminals. This segmentation allows the thick intrinsic region to be achieved while maintaining CMOS compatibility through standardized layer integration
Solution Approach 2:
The invention transitions from a conventional planar photodetector design to a vertically-stacked multi-layer architecture. By stacking the substrate, buried layer, intrinsic layer, and contact layers in the vertical dimension, the patent achieves a thick active region for photon detection while maintaining a compact footprint that enables CMOS integration and multipixel array designs
2Ease of manufacture
If a CMOS compatible process is used, then integration is improved, but thick vertical region is not allowed causing PDE to be sacrificed
Solution Approach 1:
The patent creates a multi-functional layer structure where each layer serves multiple purposes: the substrate provides mechanical support and electrical connection, the buried layer enables both electrical contact and structural stability, and the intrinsic layer provides both the active photon detection region and electrical isolation. This multi-functionality allows CMOS-compatible manufacturing while achieving thick vertical regions for high PDE
Solution Approach 2:
The photodetector employs a composite structure combining different semiconductor materials and doping types in specific layers. The intrinsic layer (undoped or lightly doped) is combined with heavily doped contact layers and a buried layer, creating a composite material system that optimizes both electrical properties for CMOS integration and optical properties for photon detection efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances Photon Detection Efficiency (PDE) by enabling the detection of longer wavelengths with improved CMOS integration and multipixel designs, achieving a PDE of about 50% for 905 nm photons, compared to conventional Silicon photomultipliers at 7%, while maintaining manufacturing flexibility.
Implementation Method 1
a portion of a surface area of the PMD layer may be configured to receive a photon
Implementation Method 2
achieving a PDE of about 50% for 905 nm photons
Data Source
AI summary
An electronics module assembly for detecting photons is provided to include: a substrate layer; a buried layer deposited upon a first surface area of the substrate layer; an intrinsic layer deposited upon a first portion of a first surface area of the buried layer; a plug layer deposited upon a second portion of the first surface area of the buried layer; a p-plus layer deposited upon a first surface area of the intrinsic layer; an n-plus layer deposited upon a first surface area of the plug layer; a pre-metal dielectric (PMD) layer deposited upon the p-plus layer and n-plus layer; a first node coupled, through the PMD layer, to the p-plus layer; and a second node coupled, through the PMD layer, to the n-plus layer.