Buried Line Fabrication Using Top-Layer Via Patterning
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Solution Overview
Problem
Existing fabrication techniques for buried lines in electronic devices, such as integrated circuits and memory devices, are inefficient as they require multiple processing steps, increased processing time, and higher fabrication costs.
Innovation Solution
The described techniques involve patterning vias at the top layer of a stack to create channels in buried layers, which are then filled with conductive material to form buried lines. This method allows for the simultaneous construction of buried lines at multiple layers and can be performed after the formation of upper layers, reducing the number of processing steps and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional fabrication techniques are used to form buried lines, then the lines can be constructed, but the number of processing steps increases and fabrication time increases
Solution Approach 1:
The patent applies preliminary action by forming the buried lines at a buried layer before forming the layers that will ultimately be above it. This allows the buried lines to be constructed in advance, eliminating the need to repeat processing steps for each layer level, thereby reducing the total number of processing steps and fabrication time while maintaining manufacturing precision
2Manufacturing precision
If traditional fabrication techniques are used to form buried lines, then the lines can be constructed, but fabrication costs increase
Solution Approach 1:
By constructing buried lines at the buried layer before forming upper layers, the patent eliminates the need to repeat masking and deposition steps for each layer level. This preliminary construction approach reduces fabrication costs while maintaining the required manufacturing precision for buried line formation
3Productivity
If buried lines are formed before upper layers, then processing steps are reduced, but the technique requires waiting for layer formation
Solution Approach 1:
The patent forms buried lines at the buried layer before forming upper layers, allowing subsequent processing to proceed without waiting for buried line construction at each level. This preliminary action increases productivity by enabling parallel processing of upper layers while eliminating time loss from repeated processing steps
Data Source
AI summary
Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.