Buried Near-Gate Local Interconnects for Precise BEOL Routing
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Solution Overview
Problem
Current interconnect structures in semiconductor devices face challenges in efficiently forming back-end-of-line (BEOL) interconnects that require precise routing and thinner conductive material interconnects to connect gate structures and source/drain regions across multiple levels, while avoiding over-etching and ensuring reliable contact.
Innovation Solution
A method involving the formation of a conductive material layer that extends through openings in an interlevel dielectric layer, with a subsequent subtractive etching process to create thinner interconnects, and the use of an up-via metallization scheme to recess the conductive metal layer, ensuring precise contact and avoiding over-etching, followed by the deposition of an ultra-low-k dielectric layer to cover the interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional dual damascene process is used to form vias and metal layers, then interconnect structures can be formed, but the conductive material interconnects are too thick and cannot be precisely routed across multiple levels
Solution Approach 1:
The patent inverts the conventional approach by first forming a thick conductive material layer that extends through openings in the interlevel dielectric layer, then using subtractive etching to remove excess material and create the desired thinner interconnect profiles. This reverse methodology enables precise routing control while starting with a robust thick conductive layer.
Solution Approach 2:
The conductive material layer is formed in advance with sufficient thickness to ensure reliable contact, then subsequent subtractive etching processes precisely remove material to achieve the final thinner interconnect dimensions. This preliminary formation of thick conductive material followed by controlled removal solves both the thickness and precision requirements.
2Manufacturing precision
If subtractive etching is used to create thinner interconnects, then routing precision is improved, but over-etching may occur causing loss of conductive material
Solution Approach 1:
The patent forms a thick conductive material layer that extends through openings in the interlevel dielectric layer and contacts the source/drain surfaces with excess material beyond the final desired thickness. This excess conductive material serves as a cushion against over-etching during subtractive etching processes, ensuring that even if etching removes more material than intended, reliable contact is maintained.
Solution Approach 2:
The patent changes the thickness parameter of the conductive material layer from thin to thick in the preliminary formation step, then uses controlled subtractive etching to reduce it to the final thinner dimension. This parameter transformation approach allows precise thickness control while maintaining a safety margin against over-etching.
3Reliability
If thicker conductive material interconnects are used, then contact reliability is improved, but routing precision and ability to connect across multiple levels deteriorates
Solution Approach 1:
The patent segments the formation process into distinct stages: first forming a thick conductive material layer for reliable contact, then using subtractive etching to create thinner routed portions. This segmentation allows different parts of the interconnect structure to have different thicknesses - thick at contact points for reliability, thin in routed portions for precision routing across multiple levels.
Solution Approach 2:
The patent creates local variations in conductive material thickness, with thicker regions at source/drain contact points ensuring reliable electrical contact, and thinner regions in the routed portions enabling precise routing and multi-level connections. This local quality differentiation resolves the contradiction between contact reliability and routing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient BEOL interconnects that are thinner in height, ensuring reliable connections between gate structures and source/drain regions, while preventing over-etching and allowing for the use of ultra-low-k dielectric layers to cover the interconnects, enhancing the structural integrity and performance of semiconductor devices.
Implementation Method 1
forming a conductive material layer on a semiconductor device, the semiconductor device comprising at least two gate structures and at least two source/drain surfaces
Implementation Method 2
forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask
Data Source
AI summary
Methods for fabricating a semiconductor device are provided. The method can include forming a conductive material layer on a semiconductor device, the semiconductor device including at least two gate structures and at least two source/drain surfaces of at least two source/drain regions, wherein an interlevel dielectric layer separates each of the at least two gate structures from each of the at least two source/drain surfaces, wherein the conductive material layer extends through openings of the interlevel dielectric layer, contacting the at least two source/drain surfaces and forming at least two conductive material interconnects, and wherein the conductive material layer extends over the interlevel dielectric layer, forming an interconnect mask over portions of the conductive material layer, wherein the conductive material layer includes an up-via and forming an interconnect by subtractively etching a portion of the conductive material layer, exposed through the interconnect mask.