A light emitting device package employs a recessed body structure to buffer thermal deformation, preventing defects while improving light extraction efficiency.
A light-emitting device uses a reflective metal member on the lower surface to redirect upward emitted photons.
An equipotential conductive film prevents silver migration in Group III nitride LED reflective films by equalizing potential differences between electrodes.
Graded silicon barriers confine carriers to boost emission efficiency while suppressing magnesium diffusion.
A vertical heterojunction transistor design using III-N semiconductor stacks to achieve high electron mobility conduction paths.
Routing field plate interconnection through inactive region reduces parasitic capacitance and stabilizes drain current.
An AlN layer under the gate raises conduction band energy to enable normally-off operation without increasing device complexity.
A p-type nitride layer injects holes into the channel region of a GaN field effect transistor.
Trenches filled with low-index insulators redirect lateral light paths to reduce reabsorption losses in ultraviolet semiconductor devices.
Segmented potting trenches filled with rigid material enhance mechanical stability in optoelectronic semiconductor components.
Thermal annealing of doping sidewall spacers forms a punch-through stop layer at the fin bottom.
Polycrystalline metal nitrides form via controlled chemical vapor deposition, resolving weak grain bonding and high porosity.
A GaN spacer enables selective etching of the InGaN cap, improving manufacturability and gate voltage reliability.
A predisposed high electron mobility transistor uses a continuous cap layer to select electrical states through bandgap and polarization differences.
Subtractive etching of a thick conductive layer creates thinner interconnects that resolve routing precision and contact reliability contradictions.
Short siloxane branches in the silicone network absorb thermal stress to prevent cracking during temperature cycling.
Segmented LED covers with varying phosphor diffusion coefficients suppress directional variation and minimize unnecessary light leakage.
Metal oxide structures fill holes in the p-type GaN layer to overcome small critical angle limitations and enhance light extraction efficiency.
Zinc blende and wurtzite phase boundaries in III-nitride LEDs suppress nonradiative Auger recombination by eliminating hole potential wells.
Segmented gate electrodes manage carrier distribution to prevent current concentration and reduce switching losses during turn-off operations.
Segmenting the cathode into a central N-well and lightly doped edge reduces on-resistance by 20% without lowering breakdown voltage.
A vertical field effect transistor method forms doped epitaxial top source and drain regions within a recessed fin channel.
Self-aligned oxide and lateral contacts replace diamond epitaxial layouts to reduce source drain resistance during fin pitch scaling.
A semiconductor device uses insulating layer protrusions to define contact hole positions within trench structures.
A recessed channel region in an ultra high voltage MOS transistor device smooths electrical field distribution.
Inclined dielectric portions embedded in a semiconductor layered body alter light propagation direction through refraction.
Leakage current control regions create a depletion barrier that reduces reverse bias leakage without increasing device complexity.
AlGaN nanowire hosts InN quantum dots to enable dislocation-free single-photon emission at 1.3 and 1.55 micrometers.
An insulating layer separates conductive structures in a trench MOSFET, reducing on-resistance without increasing parasitic capacitance.
Selective substrate removal and polishing create uneven surface structures that enhance light extraction efficiency while minimizing thermal damage.
Segmented dopant profiles increase breakdown voltage while maintaining low on-resistance, resolving the trade-off between high voltage and conduction loss.
Segmenting the back-barrier into high and low aluminum regions resolves the contradiction between electric field reduction and device capacitance.
Epitaxial growth replaces ion implantation to suppress leakage current in III-V compound semiconductor finFET devices.
A semiconductor device uses needle-shaped field plate structures to reduce parasitic capacitances.
A thin film cap with a higher band gap pulls back the valence band to reduce leakage current.
Vertical carrier lifetime zones in the substrate reduce charge carrier concentration, improving switch-off ruggedness and lowering on-state voltage drop.
An InAlGaN cap layer reduces parasitic resistance in GaN transistors.
An indirect-bandgap semiconductor LED generates light via a hot electron-hole plasma in a p-i-n structure.
A lateral double diffused metal oxide semiconductor field-effect transistor uses a finger-like field region structure to manage electrical fields.
Isolation fingers achieve a reduced surface field effect to increase breakdown voltage without requiring additional masks.
A thin film resistance layer spirals and oscillates in thickness to increase total resistance value.
Auxiliary electrode layer covers light-emitting elements to enhance display reliability.
A floating field ring termination structure optimizes semiconductor edge design.
A strain-compensated multi-quantum well structure balances lattice mismatch between InGaAs and GaAsP layers to optimize carrier confinement.
A semiconductor light emitting device package uses a silicon molding compound resin portion to reduce thermal stress between the lead frame and the chip.
Stripe-shaped gates and separation regions reduce bipolar degradation in silicon carbide devices.
A doped III-nitride light emitting layer maintains high quantum efficiency at elevated current densities.
A normally-off GaN field effect transistor uses a C-axis main surface to enable precise carrier concentration control.
An LED package eliminates carrier substrates using a direct lead frame mount, reducing thermal resistance and manufacturing costs.
A non-diffusion photodiode structure uses a specific boundary relationship between an intermediate layer and a multiplication window layer.