Semiconductor Edge Termination Isolation Fingers
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Solution Overview
Problem
Existing edge termination methods for semiconductor devices face challenges in implementing a 'reduced surface field' (RESURF) structure, particularly in the edge termination region, where ion implantation is hindered by the presence of gate metal and source metal gaps, leading to potential breakdown at lower voltages due to missing pillars.
Innovation Solution
Incorporating isolation fingers on both sides of the gate trenches in the edge termination region to achieve a RESURF effect, which reduces gate-drain capacitance and enhances breakdown voltage by connecting the edge gate trenches with the central active region's gate, thereby avoiding the need for additional masks and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to create pillars in the edge termination region, then the RESURF structure is achieved and breakdown voltage is increased, but the presence of gate metal and source metal gaps prevents implantation in critical regions
Solution Approach 1:
The patent introduces an intermediary structure (isolation fingers with insulating material) between the gate metal and the semiconductor substrate in the edge termination region. This intermediary allows the implantation process to proceed by providing a pathway for ion implantation that bypasses the blocking effect of the gate metal, while still achieving the desired RESURF effect and breakdown voltage enhancement.
Solution Approach 2:
The patent segments the edge termination region into distinct zones: regions with gate metal, regions with isolation fingers, and regions without metal. This segmentation allows different processing approaches to be applied to different zones, enabling ion implantation in the isolation finger regions while accepting that gate metal regions cannot be implanted. The segmented approach resolves the contradiction by making the manufacturing process feasible through selective implantation.
2Device complexity
If gate metal is deposited over the edge region to connect with edge gate conductor, then device integration is simplified and area is saved, but significant gate-drain capacitance is generated which impacts device performance
Solution Approach 1:
The patent applies local quality by creating isolation fingers with insulating material in specific locations within the edge termination region. These isolation fingers are strategically placed to reduce the capacitive coupling between gate and drain only in the critical edge regions, while allowing gate metal to remain in other areas for integration purposes. This localized approach reduces gate-drain capacitance without requiring complete removal of gate metal over the edge region.
3Ease of manufacture
If pillars are not provided in the gap between gate metal and source metal for isolation purposes, then the structure is simpler to manufacture, but breakdown occurs at lower voltage in this region
Solution Approach 1:
The patent introduces isolation fingers as intermediary structures in the gap regions between gate metal and source metal. These isolation fingers contain insulating material that acts as a mediator to prevent breakdown in the isolation gaps. The isolation fingers provide a controlled pathway that maintains electrical isolation while preventing the harmful breakdown effect, thus improving reliability without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the breakdown voltage and improves capacitance performance by creating a reduced surface field effect in the edge termination region, reducing the risk of breakdown and enhancing the overall performance of the semiconductor device.
Implementation Method 1
By providing the isolation fingers alternating with the gate fingers, it is possible to achieve a 'reduced surface field' ('RESURF') effect in this region.
Implementation Method 2
This can improve capacitance effects, in particular reduced gate-drain capacitance.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4) of a semiconductor field effect transistor. The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) filled with conductive material extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.