VFET Top Source/Drain Epitaxy via Fin Recessing
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Solution Overview
Problem
The challenge in vertical field effect transistor (VFET) fabrication lies in forming good junction overlap of the top source and drain terminal to the gate, which is difficult due to thinning of the high-κ gate dielectric, leading to reliability issues, and underlapping the junction increases external resistance, degrading transistor performance.
Innovation Solution
The method involves patterning a fin in a stack with doped and intrinsic layers, forming spacers and high-κ gate dielectric, recessing the fin channel while maintaining the high-κ gate dielectric coverage, and forming doped epitaxial top source and drain regions within the recessed trench to achieve an overlapping junction without exposing the high-κ dielectric, thus avoiding reliability and contamination concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the top source and drain terminal are overlapped with the gate to improve junction overlap, then the junction overlap is improved, but the high-κ gate dielectric is exposed and thinned leading to reliability issues
Solution Approach 1:
The fin channel is recessed in advance before forming the top source and drain regions. This preliminary recessing action creates space for the top source/drain formation while ensuring that the high-κ gate dielectric remains covered by the fin channel sidewalls, preventing exposure and thinning during subsequent processing steps.
Solution Approach 2:
The fin channel is divided into different regions: a recessed central portion and intact sidewall portions. This segmentation allows the central region to be lowered for top source/drain formation while the sidewall portions remain elevated to continue protecting the high-κ gate dielectric, thus resolving the contradiction between achieving junction overlap and maintaining dielectric integrity.
2Reliability
If the top source and drain terminal are underlapped with the gate to avoid exposing the high-κ gate dielectric, then the high-κ gate dielectric integrity is maintained, but the external resistance increases significantly degrading transistor performance
Solution Approach 1:
The solution transitions from a two-dimensional planar overlap/underlap decision to a three-dimensional vertical structure. By recessing the fin channel vertically while maintaining sidewall coverage, the patent achieves both overlap (for low resistance) and protection (for reliability) through vertical dimensionality, eliminating the need to choose between underlap and exposure.
3Ease of manufacture
If the fin channel is fully recessed to form the trench for top source and drain regions, then the top source and drain regions can be formed with good overlap, but the high-κ gate dielectric may be exposed and contaminated
Solution Approach 1:
The fin channel sidewalls act as an intermediary protective barrier between the recessing/epitaxy processes and the high-κ gate dielectric. By maintaining intact sidewall portions during recessing, the fin channel itself serves as the mediator that enables trench formation for easy manufacturing while simultaneously protecting the sensitive high-κ gate dielectric from contamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of VFETs with improved junction overlap without underlapping, maintaining high-κ gate dielectric integrity, reducing external resistance and enhancing transistor performance.
Implementation Method 1
forming a nitride liner along sidewalls of the trench
Implementation Method 2
a doped epitaxial layer disposed on a substrate
Implementation Method 3
depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel
Data Source
AI summary
Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.