FinFET Punch-Through Stop Layer via Annealed Spacers
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Solution Overview
Problem
Traditional FinFETs face challenges with weak gate control due to the distance of the fin bottom from the gate structure, leading to punch-through phenomena and severe short channel effects, exacerbated by low doping levels for high carrier mobility.
Innovation Solution
The method involves forming isolation structures, doping sidewall spacers, and a punch-through stop layer at the fin bottom through thermal annealing, along with a high-K metal gate to enhance gate control and reduce punch-through phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the fin structure is designed with low doping level to achieve high carrier mobility, then carrier mobility is improved, but punch-through phenomenon becomes more severe
Solution Approach 1:
The patent applies local quality by creating a punch-through stop layer with higher doping concentration specifically at the bottom region of the fin structure, while maintaining lower doping levels in the upper channel region. This localized doping approach allows the bottom region to resist punch-through while the upper region maintains high carrier mobility, resolving the contradiction between speed and reliability.
2Device complexity
If the gate structure is positioned far from the fin bottom to maintain proper device geometry, then device structure is simplified, but gate control ability becomes weak
Solution Approach 1:
The patent applies preliminary anti-action by forming a punch-through stop layer at the fin bottom before final gate operation. This pre-formed highly doped region actively counteracts the weak electric field at the fin bottom caused by the gate's distance, preventing punch-through phenomenon without requiring structural changes to the gate positioning.
3Reliability
If thermal annealing is applied to form punch-through stop layer, then doping concentration at fin bottom is increased, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the punch-through stop layer through thermal annealing of sidewall spacers at an early stage in the fabrication process, before gate and source/drain formation. This early formation integrates the punch-through protection into the existing fabrication flow without adding significant process complexity, as the annealing step can be combined with other thermal processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the doping concentration at the fin bottom, reducing the space-charge region extension and preventing punch-through phenomena, thereby improving carrier mobility and transistor performance.
Implementation Method 1
forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers
Implementation Method 2
forming a diffusion layer by thermal annealing the doping sidewall spacers
Data Source
AI summary
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins.