III-V FinFET with Epitaxial Doped Extensions
Solution Overview
Problem
Current semiconductor technologies face challenges in fabricating finFET devices with III-V compound semiconductor materials due to difficulties in forming self-aligned devices without damaging the crystal structure, and traditional extension doping methods like ion implantation are not effective, leading to inefficiencies in leakage current suppression and power consumption.
Innovation Solution
The method involves forming a semiconductor fin with an III-V compound semiconductor material, growing an epitaxially doped semiconductor channel material with higher electron mobility, and creating an undercut extension region beneath a dielectric spacer, eliminating the need for ion implantation and enabling controllable overlap of the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used for extension doping, then doping can be performed, but it is not effective for III-V compound semiconductor materials and damages crystal structure
Solution Approach 1:
The patent replaces ion implantation (mechanical/physical process) with in-situ doped epitaxial growth (chemical vapor deposition process). This substitution eliminates crystal damage caused by ion bombardment while achieving effective doping of III-V compound semiconductor materials through chemical reactions during epitaxial growth.
Solution Approach 2:
The patent changes the doping method from post-growth ion implantation to in-situ doping during epitaxial growth. This parameter change allows dopants to be incorporated into the crystal structure during growth without disrupting the crystal lattice, thereby maintaining crystal integrity while achieving effective doping.
2Ease of manufacture
If traditional planar FET structure is used, then manufacturing is simple, but leakage current increases and power consumption rises at nanometer scale
Solution Approach 1:
The patent transitions from a planar (2D) FET structure to a FinFET structure with vertical fins extending in the third dimension. This dimensional change increases the effective channel width and gate control over the channel, enabling better suppression of leakage current while maintaining manufacturability through self-aligned fabrication processes.
Solution Approach 2:
The patent segments the channel into multiple vertical fins instead of a single planar channel. This segmentation increases the total channel width and surface area for current flow while allowing the gate to control multiple channels simultaneously, improving power efficiency without complicating the manufacturing process.
3Manufacturing precision
If self-aligned devices are formed without proper doping method, then alignment precision improves, but leakage current suppression becomes inefficient
Solution Approach 1:
The patent replaces ion implantation-based doping with in-situ doped epitaxial growth, enabling effective doping in self-aligned structures. This substitution allows precise alignment to be maintained while achieving proper doping for leakage current suppression in the self-aligned FinFET extension regions.
Solution Approach 2:
The patent incorporates doping into the epitaxial growth process itself, performing doping action preliminarily during structure formation rather than subsequently. This preliminary doping action ensures that dopants are properly incorporated into the self-aligned extension regions before final device fabrication, enabling both precision alignment and effective leakage suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage current and reduces power consumption by using a selective etch and epitaxial growth to form a doped semiconductor material under the gate region, enhancing the manufacturability and performance of finFET devices.
Implementation Method 1
a semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin is located beneath the functional gate structure
Implementation Method 2
a doped semiconductor material having a higher dopant content than both the semiconductor fin and the semiconductor channel material is epitaxially grown on surfaces of the semiconductor fin
Data Source
AI summary
A semiconductor structure that includes a semiconductor fin comprising an III-V compound semiconductor material. A functional gate structure straddles a portion of the semiconductor fin. A semiconductor channel material having an electron mobility greater than silicon and comprising a different semiconductor material than the semiconductor fin and is located beneath the functional gate structure. The semiconductor channel material is present on at least each vertical sidewall of the semiconductor fin. A dielectric spacer is located on each vertical sidewall surface of the functional gate structure. A doped semiconductor is located on each side of the functional gate structure and underneath each dielectric spacer. A portion of the doped semiconductor material located beneath each dielectric spacer directly contacts a sidewall surface of semiconductor channel material located on each vertical sidewall of the semiconductor fin.