Fin FET Source Drain Resistance via Self-Aligned Oxide
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology nodes, the epi source or drain structure introduces serious issues for fin pitch scaling, particularly in tri-gate Fin FETs, due to resistance degradation and increased contact resistivity, which are not effectively addressed by existing solutions.
Innovation Solution
The manufacturing process involves forming a contact-all-around (CAA) T-Fin FET device with a self-aligned oxide layer and lateral epitaxial source and/or drain contacts, replacing the traditional diamond-shape epitaxial structure, which reduces source and drain resistance and mitigates short channel issues, allowing for lower fin pitch and higher integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional diamond-shape epitaxial source or drain structure is used, then manufacturing process is simpler, but source and drain resistance increases and contact resistivity increases
Solution Approach 1:
The source and drain structure is segmented into multiple regions: lightly-doped extension regions, heavily-doped main source/drain regions, and silicide contact regions. This segmentation allows optimization of each region's doping profile to reduce overall resistance while maintaining manufacturability through sequential processing steps
Solution Approach 2:
The patent employs composite material structures combining silicon with different doping concentrations in specific regions, and forms silicide compounds (such as cobalt silicide or tungsten silicide) on top of doped silicon regions to create low-resistance contacts. This composite approach reduces contact resistivity by combining the benefits of highly-doped silicon and conductive silicide materials
2Productivity
If device area is scaled down to increase integration density, then higher device density is achieved, but source and drain sheet resistance and contact resistivity increase
Solution Approach 1:
The patent changes the doping concentration parameter across different regions of the source and drain structure. Lightly-doped extensions (1E16 to 1E18 atoms/cm³) transition to heavily-doped main regions (1E19 to 1E21 atoms/cm³), and silicide contacts provide additional conductivity enhancement. This parameter optimization allows reduced device area while maintaining low contact resistivity
Solution Approach 2:
The structure implements a nested configuration where lightly-doped extension regions are positioned adjacent to the channel, heavily-doped main source/drain regions are formed over the extensions, and silicide contact regions are formed on top of the heavily-doped regions. This nested arrangement allows progressive doping and contact formation that reduces resistance despite area scaling
3Productivity
If fin pitch is reduced to increase device density, then higher integration is achieved, but short channel effects increase and resistance degradation occurs
Solution Approach 1:
The patent applies different doping qualities to different spatial locations: lightly-doped extensions near the channel provide good junction characteristics and reduced leakage, while heavily-doped main regions provide low series resistance. This local quality optimization allows reduced fin pitch while maintaining electrical performance and short channel control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CAA T-Fin FET structure achieves reduced source and drain resistance, lower leakage current, and improved device performance by replacing the diamond-shape epitaxial structure with a self-aligned oxide and metal contacts, enabling higher integration density and efficient fin pitch scaling.
Implementation Method 1
An oxide layer is formed over first and second surfaces exposed after the removal of the second portion of the exposed fin portion
Implementation Method 2
an epitaxial layer is formed in the laterally removed portion of the oxide layer
Data Source
AI summary
A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.