Vertical Heterojunction Transistor for High Current Density
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Solution Overview
Problem
Heterojunction transistors with vertical structure face challenges in high current density and substrate area efficiency due to complex fabrication processes and high on-state resistance, particularly when scaling beyond 50 mm^2, and limited performance with relatively low conduction current density.
Innovation Solution
A heterojunction field-effect transistor design with a substrate having adaptation layers for lattice matching, a III-N semiconductor material stack forming an electron gas layer, and a conducting element that extends from the source to the drain, allowing for high electron mobility and reduced on-state resistance, while simplifying the fabrication process by minimizing substrate removal from the epitaxy reactor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a lateral transistor structure is used to achieve high current density, then the electron gas layer width can be sufficient, but the substrate area occupied becomes large and the transistor dimensions are limited
Solution Approach 1:
The patent transitions from a lateral transistor structure to a vertical structure, changing the spatial arrangement from two-dimensional lateral extension to three-dimensional vertical stacking. This allows the current path to extend vertically through multiple semiconductor layers rather than laterally across the substrate surface, thereby achieving high current density while minimizing substrate area occupation.
2Quantity of substance
If the transistor area is increased beyond 50 mm^2 to accommodate high current density, then the current capacity increases, but the proportion of defective transistors increases significantly
Solution Approach 1:
By switching to a vertical structure, the patent enables high current capacity to be achieved through vertical stacking of semiconductor layers rather than lateral expansion. This maintains smaller transistor footprint (below 50 mm^2), thereby keeping defect proportions low while still achieving the required current capacity through the vertical conduction path.
3Area of stationary object
If a vertical structure is used to reduce substrate area, then the area efficiency improves, but the on-state resistance becomes relatively high
Solution Approach 1:
The patent employs a composite structure consisting of multiple semiconductor layers with different bandgaps (wide-bandgap AlGaN and narrow-bandgap GaN) forming heterojunctions. This composite material approach creates a vertical conduction path with high electron mobility through the heterostructure, reducing on-state resistance despite the compact vertical geometry.
Solution Approach 2:
The patent optimizes various parameters including the thickness of each semiconductor layer, the doping concentrations in different regions, and the composition ratios of AlGaN layers. By carefully controlling these parameters, the vertical conduction path achieves low on-state resistance while maintaining the compact substrate area occupation.
4Reliability
If complex fabrication processes are used to achieve vertical structure with high performance, then the transistor performance improves, but the fabrication complexity increases
Solution Approach 1:
The patent combines multiple functions into integrated structures: the vertical conduction path simultaneously provides current flow and voltage blocking, the heterojunction layers simultaneously provide carrier confinement and conduction, and the source-drain electrodes are positioned to serve both electrical contact and structural support functions. This integration reduces the number of separate fabrication steps while maintaining high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high current density with reduced substrate area occupation, lower on-state resistance, and simplified fabrication, addressing the limitations of traditional vertical transistors by optimizing the conduction path and reducing leakage currents.
Implementation Method 1
a first layer of GaN, n-doped on the rear face... A metal drain is formed under this first layer of GaN. This first layer of GaN is covered by a second layer of GaN, with n-type doping with a lower concentration. The second layer forms a prolongation through the third layer... The fourth layer of GaN is covered by a layer of AlGaN, so as to form an electron gas layer near their interface
Implementation Method 2
The fourth layer of GaN is covered by a layer of AlGaN, so as to form an electron gas layer near their interface
Data Source
AI summary
The invention concerns a heterojunction field-effect transistor comprising a stack of first and second III-N type semiconducting layers forming an electron gas or hole layer; a first conduction electrode in electrical contact with the gas layer and a second conduction electrode; a separation layer positioned vertically in line with the first electrode and under the second semiconducting layer; a third semiconducting layer arranged under the separation layer and in electrical contact with the second electrode; a conductive element in electrical contact with the gas layer and electrically connecting the third semiconducting layer and the gas layer; and a control gate positioned between the conductive element and the first conduction electrode.