Buried Recombination Layer for CMOS SEU Reduction

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Solution Overview

Problem

CMOS devices built on bulk portions of hybrid orientation technology (HOT) substrates face high single event upset (SEU) rates and latchup issues due to their sensitivity to ionizing radiation, which are not effectively addressed by existing technologies without performance or complexity penalties.

Innovation Solution

The implementation of a buried recombination layer within the bulk portion of the HOT substrate, which acts as a high-density recombination center to attract and combine charge carriers, and a latchup prevention layer to mitigate latchup in PFETs, reducing SEU rates and protecting against latchup by confining radiation-sensitive semiconductor material volumes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CMOS devices are built on bulk substrate portions of HOT substrates, then device performance is optimized through different crystal orientations, but SEU rates increase due to larger radiation-sensitive volume

Engineering Contradiction:
Improvedevice performanceVSAvoidSEU rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bulk substrate is segmented by introducing a buried recombination layer that divides the radiation-sensitive volume into two regions: above and below the recombination layer. This segmentation prevents charge collection from the entire bulk depth, effectively reducing the sensitive volume while preserving the benefits of bulk substrate device performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A buried recombination layer is introduced as an intermediary structure within the bulk substrate. This layer acts as a mediator that captures and recombines charge carriers generated by radiation, preventing them from reaching and affecting the CMOS devices above, thus reducing SEU rates without compromising device performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If PFETs are built in the bulk portion of HOT substrate with P-handler substrate, then device performance is optimized, but latchup susceptibility increases due to parasitic bipolar transistor formation

Engineering Contradiction:
Improvedevice performanceVSAvoidlatchup susceptibility
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The buried recombination layer serves as an intermediary that disrupts the formation of parasitic bipolar transistors in the bulk substrate. By introducing this layer, the continuous path required for latchup is interrupted, preventing the harmful latchup effect while maintaining PFET performance optimization.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The parasitic bipolar transistor components that cause latchup are effectively removed or neutralized by the buried recombination layer. This extraction of the harmful parasitic structure eliminates the latchup susceptibility while preserving the desired PFET device performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buried recombination layer significantly reduces SEU rates in CMOS devices on bulk HOT substrates to levels comparable to those on SOI substrates, while the latchup prevention layer effectively prevents latchup, enhancing the radiation immunity and performance of CMOS devices.

Implementation Method 1

forming at least one buried layer with a high density of recombination centers under the CMOS devices that are formed in the epitaxial semiconductor layer. The buried recombination centers attract both electrons and holes and combines them.

Methodology Applied
Scientific EffectRecombination:

Implementation Method 2

The epitaxial layer is located within the bulk portion of the HOT substrate at the same level as the buried oxide (BOX) layer and the top semiconductor layer in the SOI portion of the HOT substrate. The buried recombination layer prevents collection of charges generated below that layer at the CMOS devices above the buried recombination layer.

Methodology Applied
Scientific EffectPhysical confinement: Physical Containment

Data Source

PatentUS7521776B2Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
Publication Date: 2009.04.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7521776B2 patent drawing
  • US7521776B2 patent drawing
  • US7521776B2 patent drawing

AI summary

Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in CMOS devices thereabove. The crystalline defects in the buried recombination layer caused by the recombination center generating elements are not healed even after a high temperature anneal and serve as recombination centers where holes and electrons generated by ionizing radiation are collected by. Multiple buried recombination layers may be formed. Optionally, one such layer may be biased with a positive voltage to prevent latchup by collecting electrons.