Transistor TRIZ Cases

A CMOS radio frequency switch couples its transistor body to a bias voltage through an auxiliary switch.

Co-integrating transceivers, microcontrollers, and LED drivers on one chip reduces manufacturing costs and device complexity.

A self-powered driver circuit uses a high voltage semiconductor switch to provide auxiliary power for off-line switchers.

Integrating three dual-node devices into a single three-node structure reduces substrate area by 50% while maintaining FlexRay compliance.

A transistor structure uses oxide semiconductor layers with varying electron affinities to form channels over the same layer.

A semiconductor device merges volatile and non-volatile memory regions on a single substrate to reduce signal transfer paths.

A semiconductor device applies intrinsic stress via a dedicated liner to distort the fin structure and increase carrier mobility.

A sacrificial spacer creates an air gap around polysilicon to enable void-free contact hole filling.

A hydrogen-blocking layer retains atoms during treatment to boost electron mobility in flexible displays.

A power MOSFET device uses a gate conductor surrounding source and drain pillars to reduce footprint while maintaining high current handling.

Cavity spacers isolate gate electrodes in stacked nanowires, reducing parasitic capacitance and dopant contamination for improved device scaling.

Auxiliary transistor minimizes leakage currents to maintain stable gate voltage and desired luminance.

Uniform polysilicon deposition with dielectric spacers reduces CMP step height and improves planarization uniformity.

A dual-etch stop pattern with carbon and a distinct material layer ensures uniform dielectric film formation, preventing short-circuits in narrow spaces.

Segmenting the oxide semiconductor stack into regions with varying thicknesses suppresses parasitic channel generation during transistor miniaturization.

A semiconductor device uses stepped conductive layers to reduce switching transistor area while maintaining high memory storage density.

A light shielding member with a vertical extension blocks oblique light from reaching the charge storage unit in solid-state image pickup apparatuses.

Segmented edge fins reduce fin width variation by up to 3% and minimize threshold voltage mismatch across the active area.

Dual-cell EEPROM structures use a boost cell to stimulate programming, lowering high write voltages that cause transistor leakage and reliability issues.

Plasma treatment modifies epitaxial source-drain structures to form low-resistance metal-semiconductor compound layers.

A SiC field-effect device uses a lower band-gap anode region to form a heterojunction with the drift region.

Selective SiGe growth on inclined SiC sidewalls generates compressive strain to boost pMOS hole mobility while avoiding short channel effects.

Replacing aluminum and cobalt with tungsten-based layers prevents void formation during deposition in shrinking trenches, lowering resistance.

Stacked annular contacts use metal rings around dielectric pillars to reduce resistance between interconnect levels and semiconductor components.

Segmented overlay fins in FinFET substrates provide high contrast reference points for precise mask alignment measurements.

N-type isolation regions separate floating regions in IGBTs, suppressing displacement current and reducing switching loss.

Segmented carbon doping in the buffer layer reduces leakage current while controlling current collapse for high withstand voltage devices.

A Zener diode with an annularly surrounding anode structure guides current flow through a dedicated intermediate region to prevent charge trapping.

Segmented gate electrodes combine polysilicon and low-resistance materials to maintain conductivity while shrinking integration density.

A COA substrate uses a patterned color resist layer to position pixel electrodes at varying heights for improved light penetration.

An inorganic insulating film with nested openings blocks water ingress through bias wire contact holes, preventing leaking currents in image capturing panels.

A gate-all-around fin DMOS device uses vertical gate structures to enable high-voltage MOSFET operation in scaled substrates.

Segmenting the bulk substrate with a buried recombination layer prevents latchup and reduces single event upset rates by confining radiation-sensitive volumes.

An X-ray imaging panel merges terminal area formation with active area production using shared insulating and conductive layers.

A method for manufacturing vertical bipolar transistors integrates emitter, base, and collector regions into standard CMOS fabrication steps.

Composite active layer with carbon allotropes resolves low electron mobility trade-offs in amorphous silicon manufacturing.

A laminated oxygen-rich sub-insulation layer contacts the active layer to maintain carrier mobility in metal oxide thin film transistors.

A MOS transistor structure with a graded impurity diffusion region enhances junction and surface breakdown voltage.

An underlapped field effect transistor reduces leakage current by three orders of magnitude.

Varying epitaxial layer thickness creates mixed silicided terminals, resolving the trade-off between process complexity and device versatility.

Segmented nonlinear control gate electrodes and slit trenches reduce substrate warpage in high-density three-dimensional NAND memory devices.

Direct substrate connection eliminates multi-layered redistribution structures, reducing fabrication complexity while improving electrical reliability.

Dummy patterns in the peripheral circuit region enhance metal etch back dispersion characteristics, reducing defects and improving resistance distribution.

Amorphous composite metal oxide gate insulating films reduce leakage currents and power consumption while maintaining simple manufacturing processes.

A method etches periphery of buried silicon oxide and strained SiGe alloy layers to induce tensile stress in the silicon channel.

Disposing power lines below conductive lines reduces electromagnetic interference, enabling higher integration density without enlarging the unit cell area.

A volatile logic circuit connects multiple non-volatile elements through a common connection gate to enable selective redundancy activation.

An insulated field plate applies independent voltage to reduce on-resistance without degrading breakdown voltage or increasing device footprint.