MOS Transistor Impurity Diffusion Region for Breakdown Voltage
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in achieving high breakdown voltages for their MOS transistors, which are crucial for efficient voltage transfer and memory cell operation, particularly in high-voltage applications.
Innovation Solution
The semiconductor memory device incorporates a specific structure for MOS transistors with a channel region formed close to the gate electrode, overlapping source and drain regions, a contact region with higher impurity concentration, and an impurity diffusion region with a distinct concentration gradient, enhancing breakdown voltage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOS transistor structures are used in NAND flash memory, then the device can be manufactured with standard processes, but the breakdown voltage is insufficient for high-voltage applications
Solution Approach 1:
The patent applies local quality by creating distinct impurity concentration zones within the transistor structure. Specifically, it forms a channel region with first impurity concentration, source/drain regions with second impurity concentration, and an impurity diffusion region with third impurity concentration that is higher than both. This localized variation in impurity concentration optimizes different regions for specific functions: the channel region for carrier transport, the source/drain regions for contact, and the impurity diffusion region for enhancing breakdown voltage through field effect passivation.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration across different regions of the transistor. The channel region has a first impurity concentration optimized for threshold voltage control, the source and drain regions have a second impurity concentration for low contact resistance, and the impurity diffusion region has a third impurity concentration (higher than both) strategically positioned to enhance breakdown voltage. This multi-level parameter optimization resolves the contradiction between maintaining structural simplicity and achieving high breakdown voltage performance.
2Reliability
If high impurity concentration is used throughout the transistor to improve breakdown voltage, then breakdown voltage increases, but threshold voltage control and channel formation are degraded
Solution Approach 1:
The patent resolves this contradiction by applying local quality through spatially differentiated impurity concentrations. The channel region maintains a first impurity concentration that enables proper threshold voltage control and channel formation, while the impurity diffusion region introduces a third impurity concentration (higher than both first and second) in specific areas to enhance breakdown voltage. This localized approach ensures that high impurity concentration benefits breakdown voltage without compromising threshold voltage control in the channel region.
Solution Approach 2:
The patent uses segmentation by dividing the transistor into distinct functional regions with different impurity concentrations: the channel region for threshold voltage control, the source/drain regions for contact, and the impurity diffusion region for breakdown voltage enhancement. This segmentation allows each region to be optimized independently, enabling the channel to maintain proper electrical characteristics while the impurity diffusion region provides enhanced breakdown protection without interfering with channel operation.
3Ease of manufacture
If the impurity diffusion region is positioned close to the overlapping region, then manufacturing is simplified, but surface breakdown voltage is reduced due to high electric field concentration
Solution Approach 1:
The patent applies the intermediary principle by introducing a buffer region between the impurity diffusion region and the overlapping region. The impurity diffusion region is positioned to extend from the contact region toward the overlapping region but stops before reaching it, creating an intermediate zone. This intermediate structure acts as a mediator that gradually transitions the electric field, preventing sudden field concentration at the boundary while maintaining manufacturing feasibility through controlled implantation profiles.
Solution Approach 2:
The patent employs another dimension by considering the vertical depth profile of the impurity diffusion region in addition to its horizontal positioning. The impurity diffusion region is formed with a specific depth profile that extends vertically into the substrate, creating a three-dimensional distribution that separates the high-field region from the surface. This dimensional approach allows the impurity diffusion region to enhance bulk breakdown voltage while maintaining adequate surface breakdown voltage by avoiding direct contact with the surface overlapping region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves both junction and surface breakdown voltages, leading to increased operational reliability and efficiency in voltage transfer within the memory device.
Implementation Method 1
an impurity diffusion region of a first conductivity type formed in a partial region of one of the source region and the drain region and having a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration
Data Source
AI summary
A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.