FinFET Overlay Mark Fin Array for Alignment Metrology

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Solution Overview

Problem

Existing overlay marks for nonplanar devices, such as FinFETs, are inadequate for ensuring accurate mask alignment during manufacturing, leading to potential device performance issues or failure due to lack of sufficient contrast and resilience to manufacturing processes.

Innovation Solution

The development of advanced image metrology (AIM) overlay marks featuring an array of overlay fins on a substrate, which provide greater contrast and resilience, allowing for accurate alignment measurements and resistance to deformation during processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional overlay marks are used for nonplanar devices, then the manufacturing process can proceed, but the alignment measurement accuracy is insufficient leading to device performance issues or failure

Engineering Contradiction:
Improvealignment measurement accuracyVSAvoiddevice performance reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The overlay mark is segmented into multiple discrete fins arranged in an array pattern rather than using a single continuous structure. This segmentation provides multiple reference points for alignment measurement, improving measurement accuracy and reliability while maintaining compatibility with nonplanar device fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The overlay fins are designed with specific local characteristics including controlled height, width, and spacing to optimize contrast for alignment measurement. The fins have tailored dimensional properties that enhance their visibility and measurability while resisting deformation during subsequent manufacturing steps

Inventive Principle:
Principle #3Local quality

2Measurement precision

If overlay marks lack sufficient contrast and resilience, then the manufacturing process is simpler, but alignment accuracy deteriorates causing device failure

Engineering Contradiction:
Improvemask alignment accuracyVSAvoidoverlay mark structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The overlay fin dimensions (height, width, spacing) are optimized to achieve maximum contrast for alignment measurement. The fin parameters are specifically tuned to provide high visibility to overlay metrology systems while maintaining structural simplicity and resistance to deformation during fabrication

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If overlay marks are not resilient to manufacturing processes, then the fabrication process is less complex, but the marks deform leading to inaccurate alignment measurements

Engineering Contradiction:
Improveoverlay mark resistance to deformationVSAvoidoverlay mark alignment accuracy
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

The overlay fins are formed with predetermined dimensional characteristics and structural properties before subsequent manufacturing steps. The fins are pre-configured with optimal height, width, and spacing to ensure they maintain their shape and position during etching, deposition, and other fabrication processes, preventing deformation that would compromise alignment accuracy

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9129974B2Enhanced FinFET process overlay mark
Publication Date: 2015.09.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9129974B2 patent drawing
  • US9129974B2 patent drawing
  • US9129974B2 patent drawing

AI summary

An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.