Strained SiGe Alloy Etching for FDSOI Transistor Stress Transfer
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Solution Overview
Problem
Existing methods for constraining semiconductor layers in SOI substrates, such as those using strained SiGe layers, face challenges in stress transfer efficiency due to the presence of buried oxide layers and limitations in stress distribution across transistor structures, leading to reduced carrier mobility and electrical performance.
Innovation Solution
A method involving etching the buried silicon oxide layer and strained SiGe alloy at the periphery of the substrate, with specific thickness and molar fraction optimization, and partial etching of the substrate to enhance stress transfer and prevent dislocation issues, while maintaining the buried oxide layer to prevent dislocation propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried oxide layer is present between the silicon layer and the strained SiGe layer, then dislocation propagation to the silicon layer is prevented, but stress transfer efficiency to the channel is reduced
Solution Approach 1:
The patent introduces a specific interface structure between the buried oxide layer and the strained SiGe layer that acts as an intermediary. This interface is engineered to facilitate stress transfer while the buried oxide layer continues to block dislocation propagation, thus resolving the contradiction between reliability and stress transfer efficiency
Solution Approach 2:
The patent optimizes parameters such as the thickness of the buried oxide layer, the composition and thickness of the strained SiGe layer, and the etching depth to achieve optimal stress transfer. By carefully controlling these parameters, the system maintains dislocation prevention while maximizing stress transfer to the channel
2Device complexity
If the strained SiGe layer dimension is reduced to match the gate dimension with spacer, then transistor structure integration is improved, but the stress transmitted to the channel is reduced
Solution Approach 1:
The patent applies local quality by creating a stress profile that is concentrated in the channel region. The strained SiGe layer is positioned and dimensioned to provide localized stress enhancement exactly where needed in the channel, rather than uniform stress distribution, thus maintaining effective stress transmission despite reduced overall layer dimensions
Solution Approach 2:
The patent utilizes vertical layering and depth positioning to maintain stress transmission effectiveness. By optimizing the vertical stack configuration and etching depth, the system compensates for reduced lateral dimensions, ensuring adequate stress transmission to the channel while achieving proper transistor structure integration
3Stress or pressure
If the etching depth in the substrate is increased, then stress transfer is enhanced, but the risk of exposing the silicon layer to dislocation propagation increases
Solution Approach 1:
The patent applies partial action by performing selective etching at specific locations (peripheral zones) rather than uniform etching across the entire substrate. This localized etching approach enhances stress transfer in critical regions while maintaining the protective buried oxide layer in other areas, thus balancing stress transfer enhancement with dislocation protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases carrier mobility and electrical performance by optimizing stress distribution within the transistor channel, particularly in FDSOI transistors for advanced nodes, by inducing tensile stress in the silicon layer and maintaining high intrinsic stress in the SiGe alloy.
Implementation Method 1
transfer stress in the channel: a layer of SiGe with a Germanium concentration of 35%, in compression induces a tension in the channel just above
Implementation Method 2
act on the stresses exerted at the level of the silicon layer (or of any other semi-transparent material) of the SOI substrate, to increase the mobility of the carriers thanks to the effect of a mechanical constraint on a semiconductor material
Data Source
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Figure 3a~3c
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AI summary
The invention relates to a method for constraining a pattern having a pattern surface (W, LZA) in a layer of semiconductor material, which may be silicon, on the surface of a stack of layers prepared on the surface of a substrate, said stack comprising at least one constrained layer of SixGey alloy with x and y mole fractions, and a buried silicon oxide layer (BOX), characterized in that: - it comprises etching around the periphery of a surface with dimensions greater than those of said pattern surface, of the buried silicon oxide layer and of the SixGey alloy layer over at least a part of the depth of said alloy layer; - the buried silicon oxide layer (BOX) being located between said layer of semiconductor material, which may be silicon, and said constrained SixGey alloy layer.In the case of a transistor structure, etching the periphery of said surface makes it possible to obtain a pattern thus defined having dimensions larger than the area of interest located under the transistor gate. The invention also relates to a method for manufacturing transistors incorporating said method.