Oxide Semiconductor Stack for Transistor Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors are miniaturized, they experience deterioration in electrical characteristics such as threshold voltage and subthreshold value, leading to increased power consumption and reduced reliability, along with the generation of parasitic channels and inability to retain data when power is stopped.
Innovation Solution
A semiconductor device with an oxide semiconductor stack structure, comprising a first, second, and third oxide semiconductor layer, where the energy of the conduction band bottom of the first and third layers is closer to the vacuum level than the second layer, and the energy differences between these layers are optimized, along with specific electrode materials and layer thicknesses to improve electrical characteristics and reduce parasitic channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor miniaturization is implemented to increase integration density, then productivity and integration level improve, but electrical characteristics such as threshold voltage and subthreshold value deteriorate
Solution Approach 1:
The oxide semiconductor layer is divided into multiple regions with different thicknesses: a first region with thickness TS1≥TG1 (where TG1 is gate insulating film thickness) and a second region with thickness less than TG1. This segmentation allows different portions of the channel to have different electrical characteristics, maintaining good electrical performance while enabling miniaturization.
Solution Approach 2:
Different regions of the oxide semiconductor layer are given different thickness characteristics to optimize local electrical properties. The first region has sufficient thickness to maintain electrical characteristics, while the second region is thinner to reduce overall device size and enable higher integration density.
2Productivity
If transistor size is reduced for miniaturization, then integration density increases, but power consumption increases due to electrical characteristic deterioration
Solution Approach 1:
By segmenting the oxide semiconductor layer into regions with different thicknesses, the invention maintains adequate thickness in the first region to preserve electrical characteristics and control power consumption, while reducing overall device footprint through the thinner second region.
3Productivity
If transistor is miniaturized to increase integration, then productivity improves, but parasitic channels are generated reducing reliability
Solution Approach 1:
The varying thickness profile of the oxide semiconductor layer creates local electrical property differences that suppress parasitic channel formation. The thicker first region provides sufficient control over charge carriers to prevent parasitic channels, while the overall miniaturized structure enables high integration density.
Data Source
AI summary
A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1≥TG1.