Silicided Source/Drain Terminals for Mixed Transistor Configurations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device fabrication processes lack the flexibility to produce transistors with both fully and partially silicided source/drain terminals on the same chip, limiting the diversity of transistor configurations.
Innovation Solution
The method involves forming field-effect transistors with fully-silicided and partially-silicided source/drain terminals by varying the thickness of epitaxial semiconductor layers and using a self-aligned silicidation process to achieve both fully and partially silicided sections on the same chip, allowing for a combination of fully-silicided and partially-silicided terminals in a single structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional silicidation processes are used, then all transistors on the chip have identical silicidation levels, but the process lacks flexibility to produce both fully and partially silicided terminals
Solution Approach 1:
The patent applies local quality by creating different silicidation configurations (fully silicided vs. partially silicided) in different regions of the chip. This is achieved by varying the thickness of epitaxial semiconductor layers in specific regions before applying a uniform silicidation process, allowing each region to receive appropriate silicidation treatment without requiring separate processing steps for each transistor type.
Solution Approach 2:
The patent employs preliminary action by pre-forming epitaxial semiconductor layers with different thicknesses before the silicidation process. This preliminary structuring of the semiconductor layers with varying thicknesses enables the subsequent silicidation process to naturally produce different silicidation levels (fully or partially) in different regions, avoiding the need for complex post-silicidation modifications.
2Ease of manufacture
If uniform silicidation is applied to all transistors, then manufacturing is simplified, but device performance and configuration diversity are limited
Solution Approach 1:
The patent utilizes parameter changes by varying the thickness parameter of epitaxial semiconductor layers across different regions of the chip. This single parameter variation (layer thickness) enables the production of multiple transistor configurations (fully silicided, partially silicided) while maintaining a uniform silicidation process, thus achieving both manufacturing simplicity and device diversity.
3Adaptability or versatility
If multiple processing steps are used to create different silicidation levels, then configuration diversity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies universality by designing a single epitaxial growth and silicidation process that serves multiple functions: it simultaneously creates fully silicided regions, partially silicided regions, and maintains manufacturing simplicity. The varying thickness epitaxial layers act as a universal precursor structure that enables multiple transistor configurations without requiring separate processing sequences for each type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the concurrent fabrication of transistors with fully-silicided and partially-silicided source/drain terminals, enhancing the flexibility and performance of semiconductor devices by optimizing silicidation processes and epitaxial growth techniques.
Implementation Method 1
forming a first source/drain terminal and a second source/drain terminal of a first field-effect transistor that each include a first fully-silicided section located at and above a top surface of a semiconductor layer
Implementation Method 2
The first source/drain terminal and the second source/drain terminal each include a fully-silicided section located at and above the top surface of the semiconductor layer
Data Source
AI summary
Structures including field-effect transistors and methods of forming a structure including field-effect transistors. A first field-effect transistor includes a first source/drain terminal and a second source/drain terminal, and a second field-effect transistor includes a third source/drain terminal and a fourth source/drain terminal. The first source/drain terminal and the second source/drain terminal each include a fully-silicided section located at and above a top surface of a semiconductor layer. The third source/drain terminal and the fourth source/drain terminal each include a partially-silicided section located over the top surface of the semiconductor layer.