UL-FET ESD Device with Controllable Trigger Voltage
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Solution Overview
Problem
Existing ESD devices face challenges in achieving ultra-low current leakage while maintaining a controllable trigger voltage, often requiring higher trigger voltages that increase costs and leakage currents, and have large area footprints, making them unsuitable for energy-efficient applications like mobile devices.
Innovation Solution
The development of an underlapped field effect transistor (UL-FET) ESD device with a controllable trigger voltage, achieved by adjusting the gate voltage, capacitance, and underlap distance, which reduces leakage current and allows for dynamic control of the trigger voltage without significant cost or area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the trigger voltage of an ESD device is increased to reduce leakage current, then leakage current is reduced, but the trigger voltage becomes much higher than the operating voltage of the IC
Solution Approach 1:
The patent implements a dynamic trigger voltage adjustment mechanism that allows the ESD device to adapt its trigger voltage to match the IC's operating voltage. The trigger voltage is no longer fixed but can be dynamically controlled to be compatible with different operating voltages, resolving the contradiction between low leakage current (requiring high trigger voltage) and voltage compatibility.
Solution Approach 2:
The patent changes the trigger voltage parameter from a fixed high value to a可调 (adjustable) parameter that can be set according to the IC's operating voltage. This parameter change enables the ESD device to maintain ultra-low leakage current while ensuring the trigger voltage remains compatible with the protected circuit's operating voltage.
2Adaptability or versatility
If additional implants are used to adjust the trigger voltage, then the trigger voltage can be matched to operating voltage, but costs and leakage currents increase
Solution Approach 1:
The patent extracts and eliminates the need for additional implants that were previously required to adjust trigger voltage. By removing this unnecessary component/step, the patent avoids the increased costs and leakage currents that would result from adding more implants, while still achieving trigger voltage matching through the dynamic adjustment mechanism.
Solution Approach 2:
The patent uses a feedback mechanism that copies or senses the operating voltage and uses this information to automatically set the appropriate trigger voltage, eliminating the need for manual adjustment through additional implants. This copying approach achieves voltage matching without the penalties of added complexity and leakage.
3Loss of energy
If gated SCRs, diode strings, or SCRs with feedback loop are used to reduce leakage current, then leakage current is reduced, but area footprint and cost increase
Solution Approach 1:
The patent merges the ESD protection function with the existing FET structure, combining what were previously separate components (ESD device and transistor) into a single integrated structure. This merging achieves ultra-low leakage current without requiring additional discrete components like gated SCRs or diode strings, thereby reducing the overall device footprint.
Solution Approach 2:
The patent creates a multi-functional device where the FET serves both as a switching element and as an ESD protection device. This universal design eliminates the need for dedicated ESD structures with large footprints, as the same transistor structure provides both logic function and ESD protection with ultra-low leakage.
Data Source
AI summary
Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.