EEPROM Memory Cell Voltage Reduction via Boost Cell
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
EEPROM memories face challenges with high write voltages, which lead to reliability issues, premature aging, and increased leakage currents, limiting the development of non-volatile memory technologies and requiring a reduction in power consumption for autonomous systems.
Innovation Solution
The implementation of a memory location with two memory cells, where one acts as a 'boost cell' to stimulate the other, allowing for increased efficiency in programming or erasing by altering the voltage distribution across their oxides during erase and programming steps, thereby reducing the required voltage while maintaining efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage Vpp (10-20V) is applied for EEPROM writing operations, then programming and erasing efficiency is improved, but reliability deteriorates due to breakdown risks and premature aging of transistors
Solution Approach 1:
The patent divides the writing operation into two distinct phases: a first phase using high voltage Vpp for efficient charge injection, and a second phase using reduced voltage for verification and stabilization. This segmentation allows the system to benefit from high voltage efficiency while avoiding its harmful long-term effects on transistor reliability.
Solution Approach 2:
The writing process employs periodic voltage modulation, alternating between high voltage pulses for charge injection and lower voltage periods for verification. This periodic action pattern enables efficient programming while reducing continuous exposure to damaging high voltage levels, thereby improving transistor reliability.
2Productivity
If high voltage Vpp is applied for EEPROM writing operations, then programming and erasing efficiency is improved, but leakage currents increase dramatically above certain threshold
Solution Approach 1:
The patent segments the voltage application into controlled phases, using high voltage only during brief injection periods and transitioning to lower verification voltages. This segmentation prevents continuous high voltage exposure that would cause dramatic leakage current increases, while still achieving efficient programming during the high voltage phases.
Solution Approach 2:
The patent rushes through the high voltage application phase as quickly as possible, minimizing the duration of exposure to voltages that cause avalanche breakdown and leakage currents. The verification phase then confirms successful programming without requiring sustained high voltage, thereby reducing overall leakage.
3Reliability
If voltage Vpp is reduced to improve reliability and reduce power consumption, then transistor aging is reduced, but programming and erasing efficiency deteriorates
Solution Approach 1:
The patent employs periodic action by alternating between high voltage pulses for efficient charge injection and lower voltage verification phases. This periodic pattern ensures that during the high voltage phases, programming efficiency is maximized, while during verification phases, lower voltages protect transistor reliability and reduce power consumption.
Solution Approach 2:
The patent dynamically changes voltage parameters throughout the writing process, using high Vpp during injection phases and reduced voltages during verification. This parameter change strategy allows the system to optimize for efficiency when needed and for reliability when needed, resolving the contradiction between the two opposing requirements.
4Productivity
If write operation duration is increased to improve programming completeness, then charging efficiency is improved, but write time becomes unacceptable
Solution Approach 1:
The patent rushes through the high voltage charge injection phase as quickly as possible to complete programming efficiently, then immediately transitions to a faster verification phase. This approach avoids the need for prolonged exposure to high voltage while ensuring complete charging, thereby reducing overall write time while maintaining charging efficiency.
Solution Approach 2:
The patent segments the write operation into distinct injection and verification phases with different voltage levels and durations. The injection phase is optimized for speed and efficiency with high voltage, while the verification phase uses lower voltage but shorter duration. This segmentation allows the system to achieve complete programming without unacceptable total write times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the high write voltage needed, enhances the efficiency of data writing, and minimizes current leakages, improving the reliability and power efficiency of EEPROM memories.
Implementation Method 1
The programming or the erasing of a floating gate transistor consists of the injection or the extraction of electrical charges into/from the floating gate of the transistor by tunnel effect ("Fowler-Nordheim effect") through the gate oxide called "tunnel oxide", by means of a high voltage pulse Vpp
Implementation Method 2
when the voltage Vpp comes close to the maximum permitted voltages for the components in question, high leakage currents appear, generally by avalanche effect
Data Source
AI summary
A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.