Gate-All-Around Fin DMOS for High-Voltage 14nm Integration
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Solution Overview
Problem
Design engineers face challenges in creating FinFET technologies that can handle higher voltage levels, particularly above 2V, as the integration density of integrated circuit devices increases, making it difficult to achieve similar scaling of device parameters, especially for 14-nanometer and beyond node sizes.
Innovation Solution
The development of gate-all around fin double diffused metal oxide semiconductor (DMOS) devices, which involve forming fin structures from a substrate, implanting conductivity types to create wells and fin structures, and forming source and drain contacts, along with a gate structure that extends vertically around the fin region and laterally over the well, enabling the creation of high-voltage MOSFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET technologies are used to increase integration density and scale channel length, then chip density and scalability are improved, but the ability to handle high voltage levels (>2V) deteriorates
Solution Approach 1:
The device is segmented into multiple fins (e.g., 5-10 fins) arranged in parallel, each fin acting as an independent current path. This segmentation allows the total current capacity to scale with the number of fins while maintaining the voltage handling capability of individual fins, thus resolving the contradiction between high density and high voltage capability.
Solution Approach 2:
The invention transitions from planar 2D device architecture to 3D vertical FinFET structure with gate-all-around configuration. The gate wraps around the fin in three dimensions, providing superior electrostatic control and enabling high voltage operation while maintaining small footprint for high density integration.
2Productivity
If channel length is scaled down to increase integration density, then more devices fit on chip, but power supply voltage scaling becomes difficult
Solution Approach 1:
Different regions of the device have different doping concentrations and geometries optimized for their specific functions. The drain region has higher doping concentration for efficient carrier collection, while the channel region maintains lower doping for high voltage capability. This local optimization allows short channel length for density while preserving voltage levels.
Solution Approach 2:
The gate structure is nested around the fin in a gate-all-around configuration, with the gate dielectric and gate electrode forming concentric layers. This nested structure provides maximum gate control over the channel while minimizing the device footprint, enabling both short channel length and high voltage operation.
3Reliability
If gate structure extends vertically around fin and laterally over well, then electrostatic control and voltage capability are improved, but device complexity increases
Solution Approach 1:
The gate structure serves multiple functions simultaneously: it provides electrostatic control of the channel, defines the active device region, provides mechanical support, and enables both low-voltage logic and high-voltage power operation. This multi-functionality reduces the need for additional separate structures, managing complexity while improving performance.
Solution Approach 2:
The gate dielectric and gate electrode are formed in a predetermined sequence using standardized semiconductor fabrication processes such as atomic layer deposition and chemical vapor deposition. The gate structure is pre-configured with appropriate thicknesses and materials before final device assembly, simplifying the overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the achievement of >2V MOSFET capability in 14 nm bulk substrates and beyond, providing fully depleted, vertical gate-all-around controlled high-voltage fin-based metal oxide semiconductor devices with improved scalability and performance.
Implementation Method 1
implanting a first conductivity type in the substrate to form an N-well and n-implanted fin structures of the plurality of fin structures; implanting a second conductivity type in the substrate to form a P-well and p-implanted fin structures of the plurality of fin structures
Data Source
AI summary
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.