Semiconductor Power Line Placement for Integration Density
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing the degree of integration of semiconductor elements while reducing power consumption and addressing issues like single or short channel effects due to the reduction in element sizes.
Innovation Solution
The semiconductor device incorporates a structure with power lines disposed between the semiconductor substrate and conductive lines, reducing interference and allowing for a more compact design, with power lines extending in a direction parallel to active regions and connecting source/drain regions to conductive lines through vias, thereby improving integration and design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If power lines are disposed above conductive lines in conventional layers, then power supply is achieved, but interference between power lines and conductive lines increases and unit cell area enlarges
Solution Approach 1:
The patent applies dimensionality change by disposing power lines in the first layer (below the conductive lines in the third layer) rather than in the same layer or above the conductive lines. This vertical separation in the layer structure reduces electromagnetic interference between power lines and conductive lines while minimizing the horizontal space required, thus reducing the unit cell area.
2Productivity
If element sizes are reduced to increase integration density, then more elements fit in smaller area, but single or short channel effects increase
Solution Approach 1:
The patent employs three-dimensional structures including stacked layers (first layer with power lines, second layer with contacts, third layer with conductive lines) and vertical vias to achieve high integration density without proportionally reducing element sizes. This vertical stacking allows maintaining larger horizontal element dimensions for better channel control while increasing overall integration density through the third dimension.
Data Source
AI summary
A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and source/drain regions connected to the channel regions, a plurality of gate electrodes extending in a second direction different from the first direction to intersect the channel regions, a plurality of conductive lines electrically connected to at least one of the source/drain regions and the plurality of gate electrodes through a plurality of vias, and a power line disposed between the semiconductor substrate and the plurality of conductive lines and configured to supply a power supply voltage.