Gate Electrode Conductive Structures with Variable Cross Sections
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Solution Overview
Problem
Forming gate electrodes with small widths but low resistance is challenging in highly integrated semiconductor devices, as existing methods struggle to achieve the necessary conductivity and uniformity.
Innovation Solution
A method involving the formation of a first electrically conductive layer on a substrate, followed by selective removal to create portions with different thicknesses, and subsequent deposition and etching of a second conductive layer to define gate electrodes with equivalent thicknesses, utilizing a conductive layer with lower resistance materials like tungsten silicide to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate electrodes are made smaller in width to increase integration density, then integration density improves, but resistance increases
Solution Approach 1:
The gate electrode is divided into two distinct conductive layers: a first conductive layer (polysilicon) and a second conductive layer (low-resistance material such as tungsten silicide or cobalt silicide). This segmentation allows each layer to contribute differently to the overall electrical properties, with the second layer specifically addressing the resistance issue in narrow gate electrodes
Solution Approach 2:
The gate electrode utilizes a composite structure combining polysilicon and a low-resistance material. The polysilicon provides the foundational conductive path, while the low-resistance material layer (with resistance significantly lower than polysilicon) is deposited on top to reduce overall resistance, enabling narrow gate electrodes to maintain low resistance despite reduced width
2Adaptability or versatility
If selective removal is performed to create nonuniform thickness portions, then manufacturing flexibility improves, but manufacturing complexity increases
Solution Approach 1:
The gate electrode structure implements local quality by creating different thickness portions in different regions. A first portion has a first thickness and a second portion has a second thickness greater than the first thickness, allowing optimization of electrical characteristics for different functional requirements (e.g., memory cell transistors versus peripheral logic transistors) within the same device
Solution Approach 2:
The method performs preliminary actions by first forming the conductive layers with nonuniform thickness before final patterning. The selective removal step creates the thickness variation in advance, and subsequent etching processes then define the gate electrodes based on this pre-established thickness profile, simplifying the overall manufacturing sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of gate electrodes with low resistance and appropriate dimensions, enabling increased operation speed and integration density in semiconductor devices.
Implementation Method 1
forming a first electrically conductive layer on a substrate. This step may be preceded by a step of forming a gate insulating layer on the substrate, with the first electrically conductive layer being deposited directly on the gate insulating layer
Implementation Method 2
The first portion of the second electrically conductive layer and the first portion of first electrically conductive layer are selectively etched in sequence to define a first electrically conductive gate electrode
Data Source
AI summary
A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask.