Deep Trench Capacitor Polysilicon Layer Formation
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Solution Overview
Problem
Existing methods for forming multi-POLY Deep Trench Capacitors (DTCs) require multiple dedicated photomask exposures and etch steps, leading to topographical variations and poor chemical-mechanical polish (CMP) uniformity due to step heights between polysilicon layers, which affects the overall performance and efficiency of the capacitor structure.
Innovation Solution
A method involving the deposition of multiple polysilicon layers with uniform thickness, separated by dielectric layers, followed by a CMP process to remove excess material and a patterned etch process to expose top surfaces, reducing the need for multiple masks and improving CMP uniformity, thereby enhancing the capacitor structure's performance and reducing step height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple dedicated photomask exposures and etch steps are used to form multi-POLY DTCs, then the capacitor structure can be formed with multiple polysilicon layers, but topographical variations and poor CMP uniformity occur due to step heights between layers
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and depositing a sacrificial layer before forming the polysilicon layers. This preliminary structure allows subsequent layers to be deposited more uniformly, reducing step heights that would otherwise cause CMP uniformity issues. The mandrel and sacrificial layer are removed after serving their purpose, leaving a well-formed multi-POLY structure without the topographical variations caused by traditional sequential layer formation.
2Manufacturing precision
If multiple dedicated photomask exposures and etch steps are used for each polysilicon layer, then each layer can be precisely formed, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent merges multiple separate photomask and etch steps into a single integrated process. Instead of forming each polysilicon layer separately with dedicated masks, the invention uses one mask pattern to define all polysilicon regions, then forms all layers in sequence without intermediate masking steps. This combining of operations maintains precision while dramatically improving productivity by reducing the total number of process steps.
3Manufacturing precision
If multiple dedicated photomask exposures are performed for each polysilicon layer, then precise control of each layer is achieved, but the overall manufacturing time and process steps increase
Solution Approach 1:
The patent performs preliminary action by creating a mandrel structure and sacrificial layer that pre-defines the geometry for all polysilicon layers. This preliminary framework allows subsequent polysilicon deposition to proceed without repeated masking, as the preliminary structures guide the formation of all layers. The result is precise layer control achieved through the preliminary geometry rather than through multiple time-consuming photomask exposures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves comparable electric performance to prior art methods while reducing overall step height and CMP loading, improving the uniformity and efficiency of the capacitor structure, and can be applied to various POLY layers in DTCs for DRAM storage cells and other IC applications.
Implementation Method 1
Portions of the second POLY layer and the second dielectric layer not within the recess are removed with a CMP, etch back, or a combination of the two
Implementation Method 2
depositing a plurality of first POLY layers of uniform thickness over a bottom region and sidewalls of a recess formed within a substrate
Data Source
AI summary
The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.