SiGe Strained Channel pMOS Transistor Manufacturing
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Solution Overview
Problem
Conventional methods for improving the operation speed of p-channel MOS transistors by generating compressive strain at the channel region face challenges due to the short channel effect caused by approximating SiGe layers containing boron to the channel, which affects hole mobility.
Innovation Solution
A manufacturing method involving the formation of an n-well and gate structures on a silicon substrate, followed by the creation of recesses and the selective growth of SiC and SiGe layers, where the SiC layer is partially removed to create an inclined sidewall, allowing for the epitaxial growth of an SiGe layer that generates larger compressive strain at the channel region, thereby enhancing hole mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SiGe layers containing boron are approximated to the channel region to improve hole mobility through compressive strain, then hole mobility increases, but short channel effect occurs which degrades device performance
Solution Approach 1:
The patent segments the strain generation function by using separate SiC and SiGe layers. SiC layers provide tensile strain while SiGe layers provide compressive strain. This segmentation allows independent optimization of strain distribution without the harmful effects of boron-containing SiGe directly adjacent to the channel, thus improving hole mobility while avoiding short channel effect degradation.
Solution Approach 2:
The patent introduces SiC layers as intermediary structures between the silicon substrate and the SiGe layers. These SiC layers act as mediators that generate tensile strain in the channel region, which compensates for the compressive strain from SiGe layers, thereby controlling the overall strain distribution to improve hole mobility without causing short channel effect.
2Manufacturing precision
If SiC layer thickness is increased to generate larger tensile strain for n-channel MOS transistors, then electron mobility improves, but the layer becomes harder to selectively remove
Solution Approach 1:
The patent applies local quality by forming SiC layers with different thicknesses in different regions. The SiC layer thickness is optimized locally according to the specific requirements of n-channel MOS transistors (for electron mobility improvement) while maintaining compatibility with the selective removal process using TMAH solution, thus achieving both improved electron mobility and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases hole mobility and operation speed in p-channel MOS transistors by optimizing the strain distribution at the channel region, while also generating tensile strain for n-channel MOS transistors using SiC layers, improving electron mobility.
Implementation Method 1
mobility of carriers (electrons and holes) moving at a channel region is improved by generating a strain in a channel
Implementation Method 2
the mobility of the hole improves by generating a uniaxial compressive strain at the channel region in the p-channel MOS transistor
Implementation Method 3
optimizing the strain distribution at the channel region, while also generating tensile strain for n-channel MOS transistors using SiC layers
Data Source
AI summary
A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.