Semiconductor Package Direct Substrate Connection
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Solution Overview
Problem
Current semiconductor packages face challenges in reliability and durability, particularly in the connection and encapsulation of semiconductor chips, which can lead to inefficiencies in the fabrication process and reduced yield.
Innovation Solution
The semiconductor package design incorporates a package substrate with a connection substrate and a mold layer, featuring insulating layers and conductive structures that electrically connect the semiconductor chip to the package substrate, eliminating the need for a multi-layered redistribution structure, thereby simplifying the fabrication process and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-layered redistribution structure is used to electrically connect the semiconductor chip to the package substrate, then electrical connectivity is achieved, but the fabrication process becomes complex and time-consuming
Solution Approach 1:
The patent extracts and eliminates the redistribution structure from the package design. Instead of using multiple insulating layers and conductive patterns to achieve electrical connection, the invention directly connects the semiconductor chip to the package substrate through simplified connecting elements, removing the complex redistribution routing entirely
Solution Approach 2:
The patent inverts the conventional approach by making the package substrate itself electrically active with integrated conductive patterns, rather than relying on a separate redistribution structure on top of the chip. The substrate provides both mechanical support and electrical connection functions simultaneously
2Reliability
If a multi-layered redistribution structure is used to electrically connect the semiconductor chip to the package substrate, then electrical connectivity is achieved, but the overall process time increases
Solution Approach 1:
The patent removes the time-consuming multi-layered redistribution structure fabrication steps. By extracting this component entirely and replacing it with direct connecting elements, the invention significantly reduces the number of fabrication steps including deposition, patterning, and etching operations
Solution Approach 2:
The package substrate is pre-configured with conductive patterns and connection structures before chip mounting. This preliminary preparation of the substrate eliminates the need for subsequent complex redistribution structure fabrication, streamlining the overall process
3Adaptability or versatility
If additional redistribution structure is added to the package, then electrical routing flexibility is improved, but the fabrication yield decreases
Solution Approach 1:
The patent extracts the redistribution function from a separate multi-layered structure and integrates it into the package substrate itself. This consolidation reduces the number of independent components and interfaces, thereby improving fabrication yield while maintaining routing flexibility through substrate-level conductive design
Data Source
AI summary
A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.