Vertical Bipolar Transistor CMOS Integration
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Solution Overview
Problem
The manufacturing of vertical bipolar transistors in CMOS circuits requires numerous additional steps and resists, resulting in insufficient performance in terms of gain and frequency resistance due to doping steps optimized for CMOS transistors rather than bipolar transistors.
Innovation Solution
A method for manufacturing bipolar transistors with reduced steps and resists by forming isolating trenches, doped wells, and contacts during CMOS transistor fabrication, utilizing the same resist for well formation and adjusting doping concentrations to optimize transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional methods are used to form vertical bipolar transistors in CMOS circuits, then the transistor structure can be formed, but the manufacturing process requires a significant number of resists and additional manufacturing steps
Solution Approach 1:
The patent merges the formation of bipolar transistor structures with the existing CMOS manufacturing process. Specifically, the isolating well NISO is formed during CMOS transistor fabrication steps, and the bipolar transistor regions (emitter, base, collector) are integrated into the same process flow, eliminating the need for separate dedicated bipolar manufacturing steps and reducing the total number of resists required.
Solution Approach 2:
The patent makes the CMOS manufacturing process universal by enabling it to produce both CMOS transistors and bipolar transistors using the same process steps. The isolating well NISO serves dual purposes: isolating CMOS transistors and providing the base region for bipolar transistors. The same doping and deposition steps create structures that function for both transistor types.
2Productivity
If doping steps are optimized for CMOS transistors, then CMOS transistor fabrication is efficient, but bipolar transistor performance in terms of gain and frequency resistance is insufficient
Solution Approach 1:
The patent applies local quality by creating region-specific doping profiles within the same manufacturing process. The isolating well NISO has a doping concentration optimized for CMOS isolation, while the bipolar regions (emitter ET, base BW, collector PPW/PW) have locally optimized doping concentrations and depths tailored for high gain and frequency resistance. This allows CMOS and bipolar regions to have different local properties despite sharing the same process flow.
Solution Approach 2:
The patent performs preliminary action by forming the isolating well NISO and the bipolar transistor regions during the CMOS fabrication process itself, before final device characterization. The doping profiles and structural configurations are pre-established during manufacturing, allowing both CMOS and bipolar transistors to achieve their optimized performance characteristics simultaneously without requiring post-processing adjustments.
3Reliability
If multiple doped wells are formed to achieve high gain and frequency resistance, then bipolar transistor performance improves, but the number of resists and doping steps increases significantly
Solution Approach 1:
The patent merges multiple doping operations into unified process steps. The isolating well NISO formation is combined with the bipolar transistor region definition, and subsequent doping steps for the emitter, base, and collector are integrated into the existing CMOS process sequence. This consolidation achieves the required multi-layer doped structure while minimizing the number of separate resist applications and doping cycles.
4Reliability
If conventional bipolar transistor structures are formed in CMOS circuits, then high performance can be achieved, but significant wafer surface area is occupied
Solution Approach 1:
The patent implements nesting by placing the bipolar transistor structure within the existing CMOS circuit layout. The isolating well NISO that defines the bipolar transistor regions is formed using the same process that creates CMOS transistor isolation, effectively nesting the bipolar structure within the CMOS process framework. This allows high-performance bipolar transistors to be integrated without proportionally increasing wafer surface area consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves high-performance bipolar transistors with improved gain and frequency resistance by integrating the formation of bipolar transistors into the CMOS manufacturing process with reduced complexity and wafer surface area usage.
Implementation Method 1
forming a first well by means of a first type of doping, in the second region, producing a collector region by forming a second well by means of the first type of doping, in the first region... forming a base region by forming a third well by means of a second type of doping
Data Source
AI summary
The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.