IGBT Floating Region Isolation for Switching Loss Reduction
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Solution Overview
Problem
The generation of displacement current due to potential variations in the floating region of semiconductor devices, such as IGBTs, leads to increased switching loss, reduced breakdown strength, current fluctuation, and voltage fluctuation, which are not effectively addressed by existing structures like the GGEE and EGE structures.
Innovation Solution
A semiconductor device with a novel structure that includes hybrid cell regions, isolation regions, and a specific trench gate configuration, where the floating region is formed deeper than the trench gates and isolated by n-type isolation regions, reducing the hole discharge path and enhancing the injection enhancement effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a trench gate structure is used to reduce on resistance, then switching performance is improved, but displacement current is generated due to potential variation in the floating region, causing increased switching loss and reduced breakdown strength
Solution Approach 1:
The semiconductor device is divided into multiple cell regions (active cell regions and inactive cell regions) with alternating arrangements. Each cell region contains specific structures (trench gates, emitter regions, floating regions) that work together to manage charge distribution and reduce displacement current while maintaining switching performance.
Solution Approach 2:
The floating region acts as an intermediary structure between the active and inactive cell regions. It stores holes and modulates potential distribution to suppress displacement current generation, thereby reducing switching loss without compromising the switching performance provided by the trench gate structure.
2Strength
If the GGEE structure or EGE structure is used to suppress potential variation in the floating region, then breakdown strength is improved, but a parasitic p-type MOSFET is formed that discharges holes excessively, reducing the injection enhancement effect and increasing switching loss
Solution Approach 1:
Different regions of the semiconductor device are assigned different structures and functions. Active cell regions contain trench gates coupled to gate potential for high-speed switching, while inactive cell regions contain trench gates coupled to emitter potential for suppressing potential variation. The floating regions are strategically positioned to store holes and modulate local potential, creating localized quality variations that collectively improve breakdown strength while controlling switching loss.
3Power
If holes are stored in the floating region to enhance the injection enhancement effect, then forward saturation voltage is reduced, but potential variation generates displacement current that increases switching loss and reduces breakdown strength
Solution Approach 1:
The inactive cell regions with trench gates coupled to emitter potential create equipotential zones that suppress potential variation in adjacent floating regions. This equipotential arrangement allows holes to be stored in the floating regions for injection enhancement effect while preventing excessive potential variation that would generate displacement current and compromise breakdown strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces switching loss, improves the withstand voltage, and enhances the injection enhancement effect by minimizing hole discharge, thereby improving the overall performance of the semiconductor device.
Implementation Method 1
holes can be discharged by the parasitic p-type MOSFET to suppress the variation in potential of the floating region
Implementation Method 2
The IE effect is to increase concentration of charges stored in a drift region by suppressing hole discharge from an emitter potential electrode side while the IGBT is on
Data Source
AI summary
Performance of a semiconductor device is improved. An active cell region has a first gate electrode that extends in a Y direction and receives a gate potential, and a second gate electrode that extends in the Y direction and receives an emitter potential. A hybrid cell region including a p-type base region and an n-type emitter region is disposed in the active cell region. An n-type isolation region adjacent to the hybrid cell region in the Y direction is formed in the active cell region excluding the hybrid cell region. Hence, even if the p-type base region or a p-type floating region is formed in the active cell region excluding the hybrid cell region, such a p-type region is isolated from the base region in the hybrid cell region by the isolation region.