Field Plate Assisted Resistance Reduction in Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices have high on-resistance due to channel and drift region resistances, which limits their footprint and efficiency, especially in circuits requiring low resistance for high current handling.
Innovation Solution
A semiconductor device design featuring a substrate with a source region, drain region, and drain extension region, along with an insulation layer and a field plate that is electrically insulated from the gate and source regions, allowing independent voltage application to the field plate, thereby reducing on-resistance and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional transistor design is used, then device structure is simple, but on-resistance is high
Solution Approach 1:
The gate structure is segmented into two independent parts: a conventional gate layer and a field plate, separated by an insulation layer. This segmentation allows independent voltage control of each component, enabling the field plate to provide additional electric field control that reduces on-resistance without requiring complete redesign of the transistor structure.
Solution Approach 2:
An insulation layer is introduced as an intermediary between the gate layer and the field plate. This intermediate layer enables electrical isolation while maintaining physical proximity, allowing the field plate to influence the channel region and reduce on-resistance without direct electrical connection to the gate circuitry.
2Device complexity
If field plate is electrically connected to gate, then device complexity is reduced, but voltage control flexibility is lost
Solution Approach 1:
The gate structure is divided into electrically independent segments (gate layer and field plate), allowing separate voltage application to each. This segmentation provides voltage control flexibility by enabling independent optimization of threshold voltage (via gate layer) and on-resistance (via field plate), while maintaining a relatively simple overall device structure.
3Reliability
If transistor size is increased to reduce on-resistance, then on-resistance decreases, but device footprint increases
Solution Approach 1:
The invention changes the electrical parameters by applying independent voltages to the field plate, creating an additional electric field that modifies the charge distribution in the channel and drift region. This parameter change reduces on-resistance through enhanced electric field control rather than through geometric scaling, thereby avoiding increased device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The independent voltage application to the field plate reduces the on-resistance of the semiconductor device without degrading breakdown voltage, enabling a smaller footprint and improved performance in circuits requiring low resistance, such as those handling large currents.
Implementation Method 1
a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region
Data Source
AI summary
Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.


