Buried VBPR Contact Structure for Stacked FET Source/Drain Isolation
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in forming effective source/drain contacts for stacked FinFET and nanosheet devices, particularly in connecting the bottom source/drain region to the backside power rail without shorting the top source/drain region, due to wiring path blockage by the top device and middle of line congestion from cell height scaling.
Innovation Solution
A buried via-to-backside power rail (VBPR) contact is formed through the bottom source/drain region to the backside of the wafer, with a recessed VBPR contact buried underneath and a dielectric cap isolating it from the top source/drain region, allowing for a top source/drain contact and backside interconnect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked FET structure is formed to reduce footprint and increase transistor density, then device integration is improved, but wiring path blockage and middle of line congestion occur due to cell height scaling
Solution Approach 1:
The patent introduces a vertical via structure that extends through the stacked FET layers to reach the backside power rail, utilizing the vertical dimension to bypass the wiring blockage caused by the top device. This dimensional transition allows the bottom source/drain contact to connect to the power rail without being blocked by the top FET's wiring paths.
Solution Approach 2:
The patent segments the power rail connection into multiple parts: a frontside contact region, a vertical via portion extending through the stacked devices, and a backside power rail region. This segmentation allows independent optimization of each segment to resolve the wiring congestion issue while maintaining high transistor density.
2Device complexity
If a via is formed to connect bottom source/drain to backside power rail, then wiring blockage is resolved, but risk of shorting with top source/drain region increases
Solution Approach 1:
The patent introduces a dielectric cap as an intermediary layer between the via and the top source/drain region. This dielectric material acts as an electrical insulator, preventing direct contact between the via and the top source/drain, thereby eliminating the shorting risk while maintaining the via's connection function to the backside power rail.
Solution Approach 2:
The dielectric cap is formed in advance within the via structure before final contact formation, preemptively preventing any potential shorting between the bottom source/drain via and the top source/drain region. This preliminary protective action ensures reliability is maintained throughout subsequent fabrication steps.
Data Source
AI summary
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.