Transistor TRIZ Cases

A recessed ALD field insulating film in FinFET shallow trenches improves fillability and suppresses short-channel effects with simpler processing.

A stacked TFT gate linked through a via cuts gate resistance and RC delay, preventing wrong charging voltage in high-resolution displays.

A diffusion barrier and multi-metal gate stack protect high-k dielectric and bottom barrier layers from spacer over-etching and undercut.

Overlapping stacked gates and selective vias route different control signals without dummy gates, improving IC gate density and cell area.

A barrier layer beside the inner spacer blocks dopant diffusion and source/drain damage in GAA nanostructures, improving gate control.

Selective fluorine diffusion into replacement gate dielectrics improves leakage reliability while tuning transistor threshold voltage.

FSW spacers confine epitaxial source/drain growth in dense active regions, preventing merge and lowering parasitic capacitance.

Inert-gas heat treatment and slow cooling remove moisture from oxide semiconductor TFT layers to stabilize electric characteristics and reliability.

In-situ growth of TMD channels and metal contacts forms graded covalent interfaces that lower FET contact resistance and improve yield.

A recessed metal cap in the lower source/drain expands contact area to reduce resistance while added dielectric improves isolation in stacked FETs.

A thicker intergate insulator selectively isolates channels in a wimpy transistor stack to cut leakage current and power use with limited process impact.

A nested backside source/drain contact uses vertical routing and a single-film upper fill to cut capacitance while preserving electrical stability.

Shielding wires placed between the FD node and signal lines cut parasitic capacitance, stabilizing photosensor output and imaging quality.

FinFET well placement fits SRAM periphery transistors within bitcell pitch limits, enabling denser layouts at nanometer nodes.

A variable-width contact separation layer improves source/drain isolation and mitigates short channel effects in dense semiconductor layouts.

Varying work function adjustment layer thickness and material tunes FinFET threshold voltage while reducing offsets and etching damage.

Strategic dummy nMOS and pMOS cells beside tap cells prevent NP/PP corner abutment and avoid DRC violations in MOS IC layouts.

A thick source/drain isolation layer in a vertical wimpy transistor stack cuts leakage current and power use without major process changes.

A thicker intergate insulator enables a wimpy transistor stack with fewer active channels, cutting leakage current and power without added process complexity.

Integrating oxide TFT driver circuits on the display substrate cuts IC mounting cost, lowers contact resistance, and reduces contact holes.

Overlapping selection and buffer transistors shrink driver circuit area, enabling narrower display bezels with low power use.

Using oxide-semiconductor transistors and shared light-blocking layers, this case cuts leakage current to stabilize OLED driving and lower power use.

Graded phosphorus and arsenic silicon layers speed ESD charge transfer, cutting turn-on time and lowering voltage peaks.

Separated gate lines for series NMOS transistors cut gate capacitance and shorten switch timing in power supply control.

A pre-silicide RTA removes oxygen clusters in RFSOI substrates, lowering resistance before metal annealing forms the silicide layer.

Uniaxial strain in III-nitride heterostructures lifts the light hole band to improve hole mobility and lower threshold carrier density in LEDs and lasers.

Selective nitrogen doping in the n-type interfacial layer thins EOT to improve gate control and cut off-state leakage in GAA CMOS.

A two-part shared source/drain contact adds top, bottom, and sidewall interfaces to cut resistance and improve top epi contact reliability.

A nanosheet standard cell layout uses boundary pads and dummy gate structures to control transistor variation, improve precision, and save area.

Multiple shorter gates linked by a connector create a long-gate FinFET LDMOS structure for high-voltage use within foundry gate-length limits.

Using two photolithography stages on a stepped substrate improves pattern resolution, electrical continuity, and production yield.

Multiple switches and resistors in each LCD pixel widen viewing angle while limiting voltage leakage, noise, and contrast loss.

A wraparound source/drain contact uses a dielectric-defined void and self-aligned liner/core deposition to lower parasitic resistance.

High-temperature fluorine implantation through the S/D cavity lowers GAA gate spacer k-value, cutting parasitic capacitance with less silicon damage.

Non-uniform FET gate lengths in an RF switch stack offset layout parasitics to improve voltage handling, ON-resistance, and linearity.

A top-gate planar oxide transistor uses doped low-resistance regions and hydrogen contact to cut parasitic delay while keeping high on-state current.

Segmented gate layers in a two-transistor oxide semiconductor memory cell improve state control and data retention under high-density wiring.

Separate epitaxial regions on one substrate integrate silicon and heterostructure components in one die, cutting parasitics, area, and power.

A width-varying channel isolation structure improves integration density while suppressing short channel effects and limiting capacitance.

A vertical pillar and AlGaN/GaN heterojunction channel raise breakdown voltage and switching speed while keeping HEMT footprint compact.

Separate reflection electrodes and insulating partition walls improve front light extraction while reducing rod-shaped LED alignment defects.

A laterally offset gate with vertical prongs cuts spacer demand, enabling tighter CPP scaling while preserving gate-source/drain separation.

Laterally offset gate and source/drain bodies in a fin FET cut spacer limits, enabling tighter CPP scaling while preserving separation.

Separate sensing and gate-drive ground paths keep current feedback from pulling down GaN gate-source voltage during switching.

A gate-all-around LDMOS with nanosheet stacks improves electrostatic control for high-voltage operation at 3 nm and 2 nm CMOS nodes.

A hybrid GAA-FinFET structure uses double epitaxial channels on silicon germanium mandrels to raise current and improve process uniformity.

Precharged storage and voltage clamping let this gate drive circuit generate negative turn-off voltage at start-up to prevent false turn-on.

Atomic layer etching clears fin flanks for separate epitaxy growth, improving gate control while reducing leakage in small-pitch FinFETs.

An isolation layer forms air gaps around an I-shaped contact structure to cut parasitic capacitance without adding major process complexity.