Extended Source/Drain Contact Wraparound to Cut Parasitic Resistance

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Solution Overview

Problem

The increasing complexity and scaling down of semiconductor integrated circuits (ICs) lead to challenges in processing and manufacturing, particularly in reducing parasitic resistance and improving duty cycle ratio performance.

Innovation Solution

A source/drain contact is formed to wrap around the source/drain region, and a void is created in the source/drain region with a dielectric film instead of a contact etch stop layer (CESL). The dielectric film is hardened and treated to prepare it as a protective layer, allowing for the deposition of conductive material for the source/drain contact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional planar contact structure is used, then the manufacturing process is simpler, but the parasitic resistance is higher and duty cycle ratio performance is poorer

Engineering Contradiction:
Improveduty cycle ratio performanceVSAvoidcontact structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact structure transitions from a conventional planar (2D) configuration to a wrapped (3D) configuration that surrounds the source/drain region. This dimensional change allows the contact to make multiple contact points with the source/drain region, reducing parasitic resistance and improving duty cycle ratio performance while managing the increased structural complexity through self-aligned fabrication processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the source/drain contact wraps around the source/drain region, then parasitic resistance is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveparasitic resistanceVSAvoidcontact alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The method performs preliminary actions by first forming the source/drain region, then depositing the contact material to wrap around it in a self-aligned manner. The contact material is deposited conformally on the sidewalls and then planarized, ensuring precise alignment with the source/drain region without requiring additional alignment steps, thus reducing parasitic resistance while managing manufacturing precision requirements

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The contact structure is formed using a self-aligned process where the contact material automatically conforms to the shape and position of the source/drain region during deposition. This self-alignment mechanism eliminates the need for separate alignment operations and ensures precise positioning, reducing parasitic resistance through optimal contact geometry while simplifying the manufacturing process

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If a void is created in the source/drain region with dielectric film, then the contact deposition is facilitated, but the process complexity increases

Engineering Contradiction:
Improvecontact deposition easeVSAvoidprocess steps complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The method extracts or removes a portion of the dielectric layer to create a void space within the source/drain region. This void facilitates the deposition of contact material by providing a defined cavity that guides material placement and ensures proper contact formation. The extracted void space simplifies subsequent contact deposition while the overall process complexity is managed through integration with existing fabrication steps

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250040183A1Device having extended source/drain contact and method
Publication Date: 2025.01.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250040183A1 patent drawing
  • US20250040183A1 patent drawing
  • US20250040183A1 patent drawing

AI summary

A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source/drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source/drain region in the source/drain opening, a void being present between the source/drain region and the bottom dielectric layer; forming a dielectric layer on the source/drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source/drain contact opening that extends to and connects with the void, the source/drain contact opening exposing sidewalls of the source/drain region; forming a liner layer on exposed surfaces of the source/drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source/drain region.