Stacked Gate IC Layout for Dummy-Free Control Signal Routing

The patent merges the gate structure with the routing function by making the gate itself conductive and capable of carrying control signals. The gate electrode is extended to form routing paths, eliminating the need for separate dummy gate structures. This integration allows the gate to serve dual purposes: controlling the transistor and providing routing connectivity.

The gate structure is designed to perform multiple functions simultaneously. It acts as both the control electrode for the transistor channel and as a routing conductor for control signals. The gate electrode material and structure are configured to provide both electrical control function and interconnect function, reducing the need for additional dedicated routing elements.

The patent transitions from planar transistor arrangement to vertical stacking by placing PMOS and NMOS transistors at different depths (different z-coordinates). This three-dimensional configuration allows overlapping of transistor footprints in the planar view, effectively doubling the gate density within the same footprint area while maintaining electrical isolation through vertical separation.

The patent implements a nested structure where the PMOS transistor is positioned above the NMOS transistor in the vertical dimension. The gate electrodes, source/drain regions, and channel structures are arranged in nested layers, with upper-layer structures positioned over lower-layer structures. This nesting approach maximizes space utilization and achieves high density while maintaining functional independence of each transistor.

The patent introduces an insulating layer as an intermediary between the PMOS and NMOS gate electrodes. This insulating layer acts as a mediator that provides electrical isolation while allowing the two gates to be in close proximity or even overlapping in the planar view. The insulating material fills the space between gates and prevents unwanted electrical interaction, enabling high-density vertical stacking.

The insulating layer is strategically placed only in specific locations where electrical isolation is needed between gates, rather than uniformly throughout the entire structure. This localized application of insulation maintains electrical isolation where required while minimizing the impact on manufacturing complexity and allowing other regions to maintain simpler structures for easier fabrication.