SRAM Periphery Layout Within Bitcell Pitch Using FinFET Wells
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges arise in fabricating SRAM devices with smaller bitcells, where the cell pitch is insufficient to place two source active regions using traditional SRAM layouts.
Innovation Solution
The proposed solution involves a novel layout for SRAM cells and periphery circuits, utilizing FinFET transistors and optimizing well regions to accommodate n-type and p-type transistors within the constraints of the bitcell pitch, thereby allowing for efficient placement and operation of SRAM cells and periphery circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional SRAM layouts are used, then the layout is simple and easy to manufacture, but the cell pitch is insufficient to place two source active regions at nanometer process nodes
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D vertical architecture by implementing FinFET transistors with vertical channel structures. The source and drain regions are positioned at different vertical levels along the fin structure, enabling two source active regions to be placed within a reduced cell pitch by utilizing the third dimension (vertical space) rather than only horizontal plane space.
Solution Approach 2:
The patent nests multiple functional components within a compact vertical structure. The FinFET channel is formed within the fin structure, with source and drain regions nested at different heights. The gate structure wraps around the fin channel, creating a nested configuration that maximizes component density within the limited cell pitch while maintaining proper spacing for manufacturing.
2Quantity of substance
If bitcell size is reduced to increase device density, then higher device density is achieved, but the cell pitch becomes insufficient for traditional SRAM layouts
Solution Approach 1:
By adopting vertical FinFET structures, the patent extends the layout into the vertical dimension, allowing multiple source active regions to be accommodated within a smaller horizontal cell pitch. The vertical channel length and height of the fin structure provide additional spatial degrees of freedom, enabling higher device density without further reducing the already constrained cell pitch.
3Reliability
If n-type and p-type transistors are placed in separate well regions, then transistor performance is optimized, but the layout space requirement increases
Solution Approach 1:
The patent merges the n-type and p-type well regions into a shared common well structure. Both n-channel FinFETs and p-channel FinFETs are formed within the same well region, eliminating the need for separate well regions. This merging reduces the total layout area while maintaining proper electrical isolation and performance characteristics through careful design of the shared well structure and doping profiles.
Data Source
AI summary
A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.