Dummy And Tap Cell Layout for MOS IC DRC Corner Compliance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing layout structures for integrated circuits (ICs) face challenges with design rule check (DRC) violations at corner areas where nMOS and pMOS device layers meet, leading to manufacturing yield and performance issues.
Innovation Solution
A dummy cell and tap cell layout structure is introduced, where dummy nMOS and pMOS cells are strategically placed adjacent to p-tap and n-tap cells, respectively, to avoid corner case abutment and prevent DRC violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nMOS and pMOS devices are arranged in adjacent rows with tap cells at boundaries, then circuit functionality is achieved, but DRC violations occur at corner areas where layers meet
Solution Approach 1:
The patent introduces intermediary structures (dummy cells and extended tap cells) between the nMOS and pMOS device rows and at the boundary regions. These intermediary elements act as mediators that prevent direct corner-case abutment of NP and PP layers, thereby eliminating DRC violations while preserving the functional circuit layout. The dummy cells serve as buffer zones that maintain proper layer separation without interfering with device operation.
2Device complexity
If standard cell layout is used without dummy cells, then layout simplicity is maintained, but corner case abutment of NP/PP layers causes DRC violations
Solution Approach 1:
The patent applies preliminary action by strategically placing dummy cells and extending tap cells in advance during the layout design phase. These preliminary structural additions prevent the formation of problematic corner cases before manufacturing, ensuring that NP and PP layers never directly abut at corners. The dummy cells are positioned proactively at locations where DRC violations would otherwise occur, eliminating the need for complex post-layout corrections.
3Manufacturing precision
If dummy cells are added to prevent DRC violations, then manufacturing yield improves, but layout complexity increases
Solution Approach 1:
The patent applies local quality by introducing dummy cells and extended tap cells only in specific localized regions where DRC violations occur, rather than uniformly across the entire layout. The dummy cells are strategically placed at boundary areas between nMOS and pMOS rows and at tap cell perimeters, maintaining simple standard cell layouts in functional regions while adding complexity only where necessary to prevent corner-case abutment. This localized approach minimizes overall layout complexity while achieving DRC compliance.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A MOS IC includes a first circuit including a first plurality of nMOS devices, a first p-tap cell, and a first dummy nMOS cell, and a second circuit including a first plurality of pMOS devices, a first dummy pMOS cell, and a first n-tap cell. The nMOS/pMOS devices are spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the nMOS devices. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the pMOS devices. The pMOS devices are adjacent to the nMOS devices in a second direction orthogonal to the first direction. The first p-tap cell / the first dummy pMOS cell and the first dummy nMOS cell / the first n-tap cell are respectively adjacent to each other in the second direction.