Step-Structured Substrate Patterning Across High and Low Regions
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Solution Overview
Problem
Existing methods for manufacturing electronic devices face challenges in improving process yield and mass production efficiency under existing design constraints.
Innovation Solution
A method involving the use of a substrate with a step structure, where a pattern layer is formed using at least two photolithography processes, allowing for the creation of a pattern layer with specific unit patterns extending from high-level to low-level surfaces, ensuring precise electrical connections and insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single photolithography process is used to form the pattern layer, then the manufacturing process is simpler and faster, but the pattern layer cannot achieve precise electrical connections and high-resolution patterns across step structures
Solution Approach 1:
The pattern layer formation is divided into multiple photolithography processes (first and second photolithography processes) that are performed at different stages. The first process forms initial patterns on the high-level surface, while the second process forms additional patterns after the low-level surface is exposed, enabling precise electrical connections across step structures with different heights.
Solution Approach 2:
The first photolithography process is performed preliminarily to form patterns on the high-level surface before the low-level surface is exposed. This preliminary action ensures that patterns requiring higher precision are established first, and subsequent processes can build upon this foundation without compromising the already-formed high-precision patterns.
2Reliability
If multiple photolithography processes are used to form the pattern layer, then the pattern layer achieves better resolution and electrical connections, but the manufacturing time and process complexity increase
Solution Approach 1:
The manufacturing process is segmented into distinct photolithography stages, with each stage targeting specific electrical connection requirements. The first photolithography process establishes critical patterns for reliable electrical connections, while the second process completes the pattern layer formation, ensuring overall connection reliability without requiring all patterns to be formed in a single time-consuming process.
3Manufacturing precision
If the pattern layer is formed before exposing the low-level surface, then the high-level surface patterns are more precise, but the low-level surface cannot be properly integrated into the final structure
Solution Approach 1:
The first photolithography process is performed preliminarily on the high-level surface while it is still covered, ensuring precise pattern formation. After this preliminary action, the low-level surface is exposed and the second photolithography process is performed to integrate the low-level surface structures, achieving both high precision and proper integration of step structures with different heights.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the production yield and efficiency of electronic device manufacturing by reducing disconnection issues and improving the resolution and reliability of the pattern layer, suitable for high-resolution applications.
Implementation Method 1
The pattern layer is formed by at least two photolithography processes
Data Source
AI summary
The present disclosure provides an electronic device comprising a substrate, and an electrode. The substrate comprises a base, a first metal layer disposed on the base, a second metal layer disposed on the first metal layer and electrically connected to the first metal layer, and an insulating layer disposed on second metal layer. The electrode is disposed on the insulating layer. The substrate comprises a high-level region and a low-level region. The insulating layer comprises an opening in the low-level region to expose a part of the second metal layer. A part of the electrode is disposed in the high-level region and another part of the electrode is disposed in the low-level region.