Vertical FET Gate-Prong Layout for Tighter Contacted Poly Pitch
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Solution Overview
Problem
The miniaturization of transistors is limited by the minimal distance between the gate of two subsequent transistors, known as contacted poly pitch (CPP), which is constrained by gate length, source/drain contact area, and gate spacer width.
Innovation Solution
A field-effect transistor (FET) device with a novel architecture where the gate body is laterally offset with respect to the source and drain bodies, and the gate prongs are vertically offset with respect to the source and drain prongs, allowing for reduced separation between the gate and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FET architecture with gate and source/drain separated by spacer is used, then electrical separation between gate and source/drain is sufficient, but CPP (contacted poly pitch) cannot be scaled further due to minimum spacer length requirement
Solution Approach 1:
The patent transitions from a planar spacer-based separation to a three-dimensional configuration where gate prongs extend vertically between channel layers. This vertical dimension allows electrical separation without consuming horizontal CPP space, as the gate body is laterally offset from source/drain bodies while maintaining vertical isolation through the prong structure
Solution Approach 2:
The gate structure is segmented into multiple gate prongs that extend vertically between stacked channel layers. This segmentation allows the gate to be positioned at different lateral locations relative to source/drain regions for different channel layers, enabling reduced CPP while maintaining adequate electrical separation through the segmented prong configuration
2Length of moving object
If gate length and source/drain contact area are reduced to scale CPP, then CPP scaling is improved, but device parameters limiting further scaling are compromised
Solution Approach 1:
The patent introduces vertical stacking of channel layers and gate prongs, transforming a two-dimensional scaling problem into a three-dimensional solution. This allows CPP to be reduced in the horizontal plane while device parameters such as channel length and contact area are maintained through the vertical dimension, avoiding the manufacturing precision compromises that would result from continued planar scaling
3Length of moving object
If gate body is laterally offset from source/drain bodies and gate prongs are vertically offset, then CPP scaling is enabled by reducing spacer need, but structural complexity increases
Solution Approach 1:
The patent merges the gate body with laterally offset source/drain bodies to form an integrated structure, while gate prongs extend vertically from the gate body between channel layers. This merging reduces the need for separate spacer structures while maintaining electrical separation, thereby enabling CPP scaling without proportionally increasing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables further scaling of CPP by reducing the need for a spacer, allowing for dynamic doping and reduced short-channel effects, while maintaining effective electrical separation.
Implementation Method 1
the gate body may be configured to, when the field-effect transistor is switched to an active state, induce, in each channel layer, an electrostatic doping in the first and second common regions and a channel region extending therebetween
Data Source
Figure 1
Figure 2~3
Figure 4a~4b
AI summary
According to an aspect, there is provided a FET device (100) comprising: a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).