Top-Gate Oxide Semiconductor Transistor Layout for Low Signal Delay
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from increased signal delay due to parasitic capacitance, leading to degraded image quality, especially as screen size increases or higher resolution images are used. Additionally, these transistors occupy a larger area compared to planar transistors, making them less desirable for high-resolution and large-screen displays.
Innovation Solution
A semiconductor device with a planar type structure using an oxide semiconductor is developed, featuring transistors with a top-gate structure. The oxide semiconductor film includes impurity elements in regions not overlapping with the gate electrode, functioning as low-resistance regions and in contact with a hydrogen-containing film. This design reduces parasitic resistance and capacitance, enhancing on-state current and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor is used, then the manufacturing process is simple and manufacturing cost is low, but signal delay increases due to parasitic capacitance and image quality degrades
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode on top of the oxide semiconductor film rather than at the bottom, creating a top-gate planar transistor structure. This structural inversion reduces parasitic capacitance between the gate and source/drain electrodes while maintaining manufacturing simplicity, thereby resolving the contradiction between ease of manufacture and signal delay performance
Solution Approach 2:
The patent transitions from a vertical stacked structure (inverted staggered) to a planar structure where the gate electrode extends over the channel region in another dimension. This dimensional change allows for reduced parasitic capacitance while maintaining effective gate control, addressing both manufacturing simplicity and signal quality requirements
2Ease of manufacture
If an inverted staggered transistor is used, then manufacturing cost is low, but occupation area is larger
Solution Approach 1:
By inverting the gate position to the top and adopting a planar structure, the transistor achieves more compact layout compared to the vertical inverted staggered structure. This structural inversion reduces the occupation area while maintaining manufacturing cost effectiveness through similar fabrication processes
Solution Approach 2:
The patent merges the gate electrode structure to extend directly over the channel region in a planar configuration, reducing the need for separate vertical stacking layers. This merging of structural elements reduces the overall occupation area while maintaining manufacturing simplicity and cost efficiency
3Area of stationary object
If a planar transistor is used, then occupation area is smaller, but manufacturing process complexity increases
Solution Approach 1:
The patent adopts a planar transistor structure with the gate electrode positioned on top, which naturally reduces occupation area. By designing this planar structure to use standard fabrication sequences similar to inverted staggered transistors, the manufacturing process complexity is minimized while achieving compact footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device achieves high on-state current, low off-state current, and stable electrical characteristics while occupying a smaller area, thereby improving image quality and reducing signal delay in display devices, especially for high-resolution and large-screen applications.
Implementation Method 1
In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions.
Implementation Method 2
The regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen.
Data Source
AI summary
A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.