RF Switch Stack Layout for Higher Voltage Handling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing RF switching devices face challenges in efficiently handling high power due to parasitic effects, which limit their voltage handling capacity and increase ON-resistance, leading to degradation in linearity performance.
Innovation Solution
The implementation of a switching device with a stack of field-effect transistors (FETs) arranged in a non-uniform configuration based on their orientation relative to the radio-frequency signal path, optimizing the distribution of gate lengths and voltage across FETs to enhance voltage handling and reduce parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If switches are arranged in a stack configuration to handle higher power, then power handling capability is improved, but parasitic effects increase leading to degraded voltage handling capacity and increased ON-resistance
Solution Approach 1:
The patent applies local quality by varying the gate length of individual FETs within the stack based on their specific position and orientation relative to the RF signal path. FETs experiencing higher parasitic effects are compensated with longer gate lengths, while those with lower parasitic effects use shorter gate lengths. This localized optimization resolves the contradiction by allowing the stack to handle high power while compensating for position-dependent parasitic effects that would otherwise degrade voltage handling capacity and increase ON-resistance.
Solution Approach 2:
The patent implements parameter changes by adjusting the gate length parameter of each FET in the stack according to its orientation relative to the RF signal path. This parameter optimization compensates for layout-dependent parasitic effects, enabling the stack to achieve both high power handling capability and acceptable voltage handling capacity with reduced ON-resistance. The gate length serves as the key parameter that is modified to resolve the contradiction between power handling improvement and parasitic effect mitigation.
2Power
If a higher stack height is utilized to allow an RF switch to withstand higher power, then power handling capability is improved, but voltage handling capacity is limited due to parasitic effects
Solution Approach 1:
The patent applies local quality by implementing position-dependent gate length optimization for each FET in the stack. FETs located in positions with higher parasitic coupling to the RF signal path are assigned longer gate lengths to compensate for the resulting voltage handling degradation. This localized compensation strategy enables the stack to achieve both high power handling capability through increased stack height and maintained voltage handling capacity by counteracting position-specific parasitic effects.
Solution Approach 2:
The patent implements parameter changes by systematically varying the gate length parameter across the stack based on each FET's orientation relative to the RF signal path. This parameter optimization directly addresses the voltage handling capacity limitation imposed by parasitic effects in high-power stack configurations. By adjusting the gate length parameter, the patent enables the stack to simultaneously achieve higher power handling capability and maintain adequate voltage handling capacity.
3Power
If switches are arranged in a stack configuration, then power handling capability is improved, but ON-resistance increases due to parasitic effects
Solution Approach 1:
The patent applies local quality by optimizing the gate length of each FET in the stack according to its specific position and orientation relative to the RF signal path. FETs experiencing stronger parasitic coupling are compensated with longer gate lengths, which reduces their individual ON-resistance. This localized optimization across the stack resolves the contradiction by enabling high power handling capability while minimizing the cumulative ON-resistance that would otherwise result from parasitic effects in series-connected FETs.
Solution Approach 2:
The patent implements parameter changes by adjusting the gate length parameter of each FET based on its orientation relative to the RF signal path. This parameter optimization directly addresses the ON-resistance increase caused by parasitic effects in stack configurations. By systematically varying the gate length parameter, the patent enables the stack to achieve both improved power handling capability and reduced ON-resistance, thereby minimizing energy loss while maintaining high power handling capability.
Data Source
AI summary
Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.