Wimpy Transistor Stack Isolation for Leakage Current Reduction
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Solution Overview
Problem
Existing integrated circuit devices face challenges in reducing leakage current and power consumption, particularly in multi-channel transistor structures where complexity and process restrictions limit the reduction of channel number or width.
Innovation Solution
The implementation of a 'wimpy transistor stack' configuration, where the thickness of the source/drain isolation layer or the intergate insulator is adjusted to electrically isolate channels, reducing current flow and thereby minimizing leakage current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistors are scaled down to increase device density, then more transistors can be packed in a given area, but manufacturing precision and control over transistor characteristics deteriorate
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertically stacked three-dimensional transistor structures. Multiple transistors are stacked in the vertical dimension to achieve high device density without further scaling lateral dimensions, thereby maintaining manufacturing precision while increasing productivity.
Solution Approach 2:
The transistor structure is segmented into distinct functional layers including channel regions, source/drain regions, and isolation layers. This segmentation allows independent optimization and precise control of each region's characteristics while maintaining overall device performance.
2Length of stationary object
If source/drain isolation layers are made thinner to reduce overall device thickness, then device profile is improved, but isolation effectiveness and prevention of leakage current worsen
Solution Approach 1:
The isolation layer is formed as a composite structure combining first and second isolation materials with different properties. The first isolation material provides thin profile and good etch selectivity, while the second isolation material provides enhanced isolation effectiveness and leakage prevention, achieving both thin profile and reliable isolation.
Solution Approach 2:
Different regions of the isolation layer are assigned different materials with specialized properties. The first isolation material is optimized for specific local requirements (thin profile, etch selectivity) while the second isolation material addresses other local requirements (isolation effectiveness), allowing each material to perform optimally for its specific function.
3Ease of manufacture
If conventional etching processes are used to form transistor structures, then manufacturing process is simpler, but etch selectivity and control over vertical sidewalls worsen
Solution Approach 1:
The etching process is segmented into multiple sequential etching steps, each targeting specific regions or materials. This allows different etching conditions to be applied to different layers, achieving precise vertical sidewall control while maintaining overall process manufacturability through systematic approach.
Solution Approach 2:
An intermediary etching layer or barrier layer is introduced between the etching process and the critical transistor structures. This intermediary layer provides etch selectivity and protects underlying structures during etching, enabling precise vertical sidewall formation without compromising ease of manufacture.
Data Source
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AI summary
An integrated circuit device includes a wimpy transistor stack (TSw_1) on a substrate (100), wherein the wimpy transistor stack (TSw_1) comprises: an upper transistor comprising: a plurality of upper channel regions (402a) stacked in a vertical direction (Z); and an upper source/drain region (404a, 404b) that contacts at least one of the plurality of upper channel regions (402a); a lower transistor that is between the substrate (100) and the upper transistor and comprises: a plurality of lower channel regions (202a) stacked in the vertical direction (Z); and a lower source/drain region (204a, 204b) that contacts at least one of the plurality of lower channel regions (202a); and a source/drain isolation layer (302a) separating the upper source/drain region (404a, 404b) from the lower source/drain region (204a, 204b), wherein the source/drain isolation layer (302a) contacts a lowermost one of the plurality of upper channel regions (402a) and/or an uppermost one of the plurality of lower channel regions (202a).