Source/Drain Formation With FSW Spacers to Prevent Feature Merge
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Solution Overview
Problem
Aggressive scaling down of IC dimensions leads to densely spaced active regions, causing source/drain features to merge, resulting in electrical issues and increased parasitic capacitance due to dielectric fins.
Innovation Solution
The method involves forming fin sidewall (FSW) spacers in semiconductor structures to confine the epitaxial growth of lower source/drain features, preventing their merge while providing sufficient volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling down of IC dimensions is performed, then production efficiency increases and costs decrease, but source/drain features merge leading to electrical issues
Solution Approach 1:
The patent divides the source/drain region into multiple segments by introducing sacrificial structures between adjacent source/drain features. These sacrificial structures act as temporary dividers that prevent merging during epitaxial growth, and are subsequently removed to create isolated source/drain regions. This segmentation approach enables continued scaling while maintaining electrical isolation.
Solution Approach 2:
The patent performs preliminary formation of sacrificial structures before epitaxial growth of source/drain features. These sacrificial structures are placed in advance to define the boundaries of source/drain regions, preventing unwanted merging during the growth process. This preliminary action ensures proper spatial separation is maintained throughout fabrication.
2Reliability
If dielectric fins are implemented to isolate adjacent source/drain features, then merging is prevented, but parasitic capacitance increases leading to degraded device performance
Solution Approach 1:
The patent extracts and removes the sacrificial structures after they have served their isolation function during epitaxial growth. By taking out these temporary sacrificial structures and replacing them with air gaps or voids, the solution eliminates the dielectric material that would otherwise create parasitic capacitance, while maintaining the physical separation between source/drain features.
Solution Approach 2:
The patent utilizes air gaps and voids (effectively porous structures) between adjacent source/drain features instead of solid dielectric fins. These air gaps provide electrical isolation with minimal parasitic capacitance, as air has a dielectric constant close to 1, significantly reducing capacitive coupling between neighboring features.
3Productivity
If source/drain features are formed in densely spaced active regions, then functional density increases, but features merge causing electrical issues
Solution Approach 1:
The patent introduces sacrificial structures as intermediary elements between adjacent source/drain features during the fabrication process. These intermediaries provide temporary physical barriers that maintain precise spacing during epitaxial growth, ensuring manufacturing precision is achieved even at high functional densities. The intermediaries are later removed, leaving no residual material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the merge of adjacent source/drain features, reduces parasitic capacitance, and ensures satisfactory source/drain feature volumes, thereby enhancing device performance.
Implementation Method 1
depositing a dielectric film over the workpiece
Implementation Method 2
performing an etching process to etch back portions of the dielectric film
Implementation Method 3
forming an epitaxial source/drain feature in the source/drain trench
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.