Nanosheet Standard Cell Layout for Transistor Variation Control
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Solution Overview
Problem
The increasing off-current due to excessive scaling in semiconductor integrated circuits leads to significant power consumption, and existing technologies lack effective methods to control variations in transistor performance and manufacturing precision.
Innovation Solution
A layout structure for semiconductor integrated circuit devices using nanosheet FETs, where standard cells are arranged side by side with specific configurations of gate interconnects, dummy gate interconnects, pads, nanosheets, and dummy nanosheets to control variations in transistor performance and manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If scaling down of gate length is continued to improve integration degree and operating speed, then transistor performance improves, but off current increases significantly leading to higher power consumption
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional nanosheet FETs, changing the dimensional structure of the channel. Multiple nanosheets are stacked vertically to form the channel, enabling better gate control and reduced off-current while maintaining scaling benefits for operating speed.
Solution Approach 2:
The patent employs composite material structures including semiconductor layers, sacrificial layers, and nanosheet formations with specific material compositions. This allows optimization of transistor characteristics to achieve both high speed operation and low off-current through material property engineering.
2Manufacturing precision
If dummy pads are added to control transistor performance variations, then manufacturing precision improves, but device area increases
Solution Approach 1:
The patent merges the functions of dummy pads with actual circuit pads by strategically positioning pads at standard cell boundaries that serve both as electrical connections and as performance control elements. This integration eliminates the need for separate dummy pads, controlling transistor variations without increasing area.
Solution Approach 2:
The pads positioned at standard cell boundaries serve multiple functions: they provide electrical connections for circuit operation and simultaneously act as dummy pads to control transistor performance variations. This multi-functionality resolves the area increase problem while maintaining manufacturing precision.
3Loss of energy
If nanosheet FET structure is implemented to reduce off current, then power consumption decreases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the channel into multiple discrete nanosheets formed by alternating semiconductor and sacrificial layers. This segmentation enables better gate control over the channel, reducing off-current while the modular layer structure facilitates systematic manufacturing through repeated deposition cycles.
Solution Approach 2:
The patent uses sacrificial layers that are formed preliminarily during the manufacturing process to define nanosheet positions. These sacrificial layers are later removed to release the nanosheets, enabling controlled formation of the three-dimensional structure without requiring complex direct nanosheet placement techniques.
Data Source
AI summary
A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.