Oxide Semiconductor Memory Cell Layout for Parasitic Capacitance Control
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Solution Overview
Problem
As the density of memory cells in memory devices increases, the distance between wirings connected to transistors decreases, leading to increased parasitic capacitance, which can make it difficult to control the conduction states of transistors and retain stored contents for a long time.
Innovation Solution
A memory device is designed with a novel structure that includes a memory cell comprising two transistors, each with specific layers of oxide semiconductor, conductive, and insulating materials. The device controls the electrical characteristics of the transistors by supplying different potentials to the conductive layers functioning as gate electrodes, allowing for effective write, retention, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased by stacking element layers, then memory capacity is improved, but parasitic capacitance increases making it difficult to control transistor states
Solution Approach 1:
The gate electrode is divided into multiple independent conductive layers (first conductive layer, second conductive layer, third conductive layer) that can be controlled separately. This segmentation allows independent voltage application to different gate regions, enabling precise control of transistor channels despite increased parasitic capacitance from high-density stacking.
Solution Approach 2:
Different voltage parameters are applied to different conductive layers during write and read operations. The first conductive layer receives a first potential, the second conductive layer receives a second potential, and the third conductive layer receives a third potential, where these potentials differ between write and read modes. This parameter change strategy optimizes transistor control for each operation type while maintaining stability against parasitic capacitance effects.
2Quantity of substance
If the distance between wirings is shortened to increase density, then memory capacity is improved, but parasitic capacitance increases causing difficulty in retaining stored contents
Solution Approach 1:
The gate electrode is segmented into multiple conductive layers that can be independently controlled. During data retention, specific voltage combinations are applied to these layers to maintain transistor off-states, preventing leakage current and preserving stored data despite reduced wiring distances and increased parasitic capacitance.
Solution Approach 2:
The patent applies different voltage parameters to different conductive layers during retention operations. By maintaining specific potential differences between layers, the transistor channels remain properly biased in the off-state, ensuring long-term data retention even when wiring distances are shortened for high-density configurations.
Data Source
AI summary
A memory device with a novel structure. A first transistor includes a first oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, and a second insulating layer. A second transistor includes a second oxide semiconductor layer, the first conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, a third insulating layer, and a fourth insulating layer. In a plan view, the first oxide semiconductor layer includes a region facing the first conductive layer with the first insulating layer therebetween and a region facing the second conductive layer with the second insulating layer therebetween. In a plan view, the second oxide semiconductor layer includes a region facing the fifth conductive layer with the third insulating layer therebetween and a region facing the sixth conductive layer with the fourth insulating layer therebetween. The first oxide semiconductor layer is provided in contact with the third conductive layer and the fourth conductive layer. The second oxide semiconductor layer is provided in contact with the first conductive layer and the seventh conductive layer. In a cross-sectional view, the third conductive layer includes a region overlapping with the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer.