Shared Source/Drain Contact Layout for Stacked Transistor Resistance
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Solution Overview
Problem
Current approaches for forming shared source/drain contacts in vertically stacked transistors face issues such as unreliable top epi contacts and poor contact resistance due to suboptimal contact areas.
Innovation Solution
A semiconductor structure with a shared source/drain contact that includes a first portion directly contacting the top surface and bottom surface of the transistors, and a second portion contacting the inner sidewall of the second transistor, thereby increasing contact areas and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shared source/drain contact is formed with conventional approaches, then the contact structure is simple, but the contact resistance is poor and the top epi contact reliability is low
Solution Approach 1:
The contact structure transitions from a conventional planar contact to a multi-dimensional structure with first and second portions extending in different directions. The first portion contacts the top surface and bottom surface vertically, while the second portion extends laterally to contact the inner sidewall, creating a three-dimensional contact geometry that increases total contact area and improves reliability without excessive complexity
Solution Approach 2:
The shared source/drain contact is divided into two distinct portions: a first portion that contacts the top surface and bottom surface, and a second portion that contacts the inner sidewall. This segmentation allows each portion to optimize its contact function independently, with the first portion providing vertical contact paths and the second portion providing lateral support and additional contact area, thereby resolving the contradiction between simplicity and reliability
2Reliability
If the bottom epi contact uses only half of the available size, then the contact structure remains compact, but the contact resistance increases
Solution Approach 1:
The contact structure utilizes vertical and lateral dimensions simultaneously. The first portion extends vertically to contact both top and bottom surfaces, while the second portion extends laterally to contact the inner sidewall, effectively using available space in multiple dimensions to maximize contact area without increasing the footprint, thereby reducing contact resistance while maintaining compactness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces contact resistance by increasing the contact areas between the source/drain regions and the shared contact, while also enhancing the reliability of the top epi contact.
Implementation Method 1
a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region
Implementation Method 2
The trench anchor of epitaxial SiGe provides additional contact areas between the first S/D contact and the first S/D region of the first transistor, thereby further helps reduce contact resistance
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.