Stacked TFT Gate Structure for Lower RC Delay in Array Substrates
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Solution Overview
Problem
Conventional array substrates suffer from excessively high resistance-capacitance delay, leading to wrong charging voltages and abnormal displaying due to increased gate resistance with higher resolution demands.
Innovation Solution
The array substrate design includes a thin film transistor layer with a first and second gate electrically connected through a through hole in a first insulating layer, reducing gate resistance by effectively increasing the gate thickness without the complexity of etching a single thick metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gate proportion in TFT is increased to meet higher resolution demands, then the resolution is improved, but the resistance-capacitance delay is increased many times
Solution Approach 1:
The patent transitions from a single-layer gate structure to a stacked multi-layer gate structure, adding the vertical dimension to reduce gate resistance. By stacking multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) vertically, the effective gate thickness increases while maintaining planar layout, thereby reducing resistance-capacitance delay without increasing horizontal space occupation.
Solution Approach 2:
The patent implements nested gate structures where multiple gate electrodes are stacked within the same horizontal footprint. The first gate electrode is positioned at a first height, the second gate electrode at a second height, and the third gate electrode at a third height, creating a nested vertical arrangement that reduces resistance without expanding the device area.
2Measurement precision
If the gate proportion in TFT is increased to meet higher resolution demands, then the resolution is improved, but the wrong charging voltage becomes excessively high resulting in abnormal displaying
Solution Approach 1:
The stacked gate structure adds vertical dimension to distribute the gate function across multiple layers, reducing the resistance-capacitance delay that causes abnormal charging voltages. The multiple gate electrodes at different heights work collectively to control the liquid crystal more efficiently, preventing excessive voltage buildup.
3Reliability
If a single thick metal layer is etched to increase gate thickness, then the gate resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent divides the gate structure into multiple separate gate electrodes (first, second, and third gate electrodes) positioned at different heights. Each gate electrode can be formed through separate deposition and etching processes, avoiding the difficulty of etching a single thick metal layer while achieving the same resistance reduction effect.
Solution Approach 2:
Instead of increasing gate thickness in the vertical direction through a single thick layer, the patent uses multiple thin layers stacked at different heights. This approach achieves equivalent resistance reduction while using standard thin-film deposition and etching processes that are easier to control and manufacture.
Data Source
AI summary
An array substrate, a method for manufacturing an array substrate, and a display panel are provided. The array substrate includes a substrate and a thin film transistor layer arranged on the substrate. The thin film transistor layer includes a plurality of thin film transistors. The thin film transistors each include an active layer, a source/drain, a first gate, a second gate, and a first insulating layer. The first gate and the second gate are electrically connected through the through hole. The problems of difficulty in etching and excessively long etching time are avoided while reducing the gate resistance of the thin film transistor.