Multi-Gate FinFET LDMOS Layout for Long-Gate High-Voltage Operation
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Solution Overview
Problem
Foundries face challenges in producing long gate lengths for FinFET LDMOS transistors due to processes like self-aligned contact (SAC), limiting their ability to meet high voltage application requirements.
Innovation Solution
The semiconductor device employs multiple shorter gates to form a long gate, with a connector physically connecting the gates, allowing for high voltage applications without the need for long gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a long gate length is used in FinFET LDMOS transistors to meet high voltage application requirements, then the power handling capability is improved, but the manufacturing complexity increases and foundries cannot produce it due to process limitations like self-aligned contact
Solution Approach 1:
The long gate is segmented into multiple shorter gate sections (first gate, second gate, third gate) that are connected in series. Each gate section has a length that can be manufactured using standard foundry processes, while their combined length provides the equivalent electrical characteristics of a single long gate, enabling high voltage operation without requiring a single excessively long gate structure
Solution Approach 2:
Connector structures are introduced as intermediary elements to physically and electrically connect the multiple gate sections together. These connectors serve as mediators that bridge the gap between separate gate sections, allowing them to function as a unified long gate while avoiding the need to manufacture a single long gate structure that exceeds process capabilities
2Adaptability or versatility
If multiple shorter gates are used to form a long gate, then the manufacturing flexibility is improved, but the device complexity increases
Solution Approach 1:
Multiple gate sections and connector structures are merged to form an integrated gate assembly that functions as a single long gate. The merging process combines the functional elements into a unified structure that achieves the desired electrical characteristics while maintaining manufacturability through standardized process steps
Data Source
AI summary
Novel semiconductors and fabrication techniques are provided. In various embodiments, a semiconductor includes a source, a drain, a first gate, a second gate, and a channel. The second gate is electrically coupled to the first gate. The first gate and the second gate are configured to control current between the source and the drain. The channel is in contact with the first gate and the second gate. The channel is configured such that the current flows through the channel. Other aspects, embodiments, and features are also claimed and described.