Series NMOS Gate Segmentation for Faster Power Switching
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Solution Overview
Problem
Existing semiconductor devices with switches, such as those used in automobile electronic control units, have long switching periods due to large gate capacitances of MOS transistors, which hinders efficient power supply management.
Innovation Solution
A semiconductor device configuration that includes two NMOS transistors in series, with their gate electrodes connected to electrically separated lines, allowing for a charge pump circuit to generate a voltage that efficiently turns on and off the transistors, thereby reducing switching time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two MOS transistors share a common gate electrode to form a switch, then the device structure is simplified, but the gate capacitance becomes large resulting in a long switching period
Solution Approach 1:
The common gate electrode is divided into two separate gate electrodes (first gate electrode and second gate electrode), each connected to its own gate line. This segmentation allows independent control of each transistor's gate capacitance, enabling faster switching by charging/discharging smaller individual capacitances rather than a larger combined capacitance.
2Reliability
If a long switching period is used to charge and discharge the gate capacitance, then the MOS transistors can be properly controlled, but the power supply management efficiency is reduced
Solution Approach 1:
The gate lines are pre-configured with separate charge pump circuits that can quickly charge the gate capacitance to the required voltage level before switching is needed. This preliminary preparation of charge pathways enables rapid transistor activation without requiring long charging periods during normal operation.
Data Source
AI summary
A semiconductor device including a first line configured to receive a power supply voltage, a second line configured to be coupled to a load of the semiconductor device, first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor, a third line coupled to the gate electrode of the first MOS transistor, and a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other.