Metal Gate Stack Structure to Prevent High-k Etch Erosion
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Solution Overview
Problem
In the fabrication of high-k metal transistors, issues such as over-etching or undercut during the formation of spacers on the sidewalls of gate structures lead to erosion in high-k dielectric layers and/or bottom barrier metals, affecting device performance.
Innovation Solution
A method for fabricating semiconductor devices involves forming a substrate with defined regions, depositing a bottom barrier metal layer, a work function metal layer, and a diffusion barrier layer, and then forming additional work function and low resistance metal layers to create a stable gate structure that mitigates etching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then fabrication process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple metal layers (first work function metal layer, second work function metal layer) combined with high-k dielectric material. This composite structure replaces conventional polysilicon gate, eliminating boron penetration and depletion effects while enabling better device performance and lower operating voltage.
2Ease of manufacture
If spacer formation is performed during high-k metal transistor fabrication, then gate structure is formed, but over-etching or undercut occurs causing erosion in high-k dielectric layer and bottom barrier metal
Solution Approach 1:
The patent forms a protective capping layer (nitride layer or oxide layer) over the high-k dielectric layer and bottom barrier metal before performing spacer formation and etching processes. This preliminary protective action prevents over-etching and undercutting from reaching and eroding the critical high-k dielectric layer and bottom barrier metal, ensuring manufacturing precision while enabling gate structure formation.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.