GAA LDMOS Nanosheet Structure for Scaled High-Voltage CMOS
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Solution Overview
Problem
Fin-based field effect transistors (LDMOS) have struggled to scale with advancing CMOS process nodes, particularly at 3nm and 2nm nodes, due to limitations in their structural scalability.
Innovation Solution
The implementation of a Gate All-Around (GAA) Laterally-Diffused Metal-Oxide Semiconductor (LDMOS) field effect transistor (FET) configuration, which includes nanosheet stacks and epitaxial layers, allows for improved scalability and performance without requiring changes in the existing process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistor structures are used, then manufacturing process is simpler, but device performance and scaling capability deteriorate
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional structure where the gate wraps around the channel in all directions (gate-all-around configuration). This dimensional change enables superior electrostatic control and scaling without proportionally increasing process complexity, as the GAA architecture can be fabricated using modified conventional semiconductor manufacturing techniques including epitaxial growth and selective etching.
2Area of moving object
If device dimensions are reduced for scaling, then integration density improves, but control over channel and electrostatic performance deteriorates
Solution Approach 1:
By implementing gate-all-around architecture where the gate electrode completely surrounds the channel in three dimensions, the patent achieves superior electrostatic control compared to planar structures. This dimensional change allows the gate to control the channel from all directions (top, bottom, and sides), providing enhanced field effect and better performance control even as device dimensions are reduced for higher integration density.
Solution Approach 2:
The patent employs composite material structures including different semiconductor materials (e.g., SiGe source/drain regions with silicon channel), multiple gate dielectric layers, and various metal layers for gates and contacts. These composite structures enable optimized electrostatic control, carrier mobility, and thermal management, allowing simultaneous achievement of scaling and reliable channel control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This GAA LDMOS FET configuration enables high-voltage operation at advanced CMOS process nodes, enhancing direct current (DC) performance and reducing short channel effects, thereby overcoming the scalability limitations of fin-based structures.
Implementation Method 1
a channel formed in the semiconductor layer between the source and drain regions, wherein the channel is controlled by a gate electrode
Implementation Method 2
a first epitaxial layer disposed on the substrate on a first side of the gate and at least part of the two or more first sheets
Data Source
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AI summary
A gate all-around laterally diffused metal-oxide semiconductor device is provided. An apparatus (100, 200, 300, 400) includes a substrate (120, 280, 320, 480), two or more first sheets (125a-125d, 255, 325a-325d, 455) disposed on the substrate (120, 280, 320, 480), a gate (110, 240, 310, 440) disposed on the substrate and at least part of the two or more first sheets (125a-125d, 255, 325a-325d, 455), and a first epitaxial layer disposed on the substrate (120, 280, 320, 480) on a first side of the gate (110, 240, 310, 440) and at least part of the two or more first sheets (125a-125d, 255, 325a-325d, 455). At least part of the two or first more sheets extends longitudinally from the gate (110, 240, 310, 440) to the first epitaxial layer.