FET Fin Structure With Lateral Offset Gate for CPP Scaling
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Solution Overview
Problem
The miniaturization of transistors is limited by the minimal distance between the gates of subsequent transistors, known as contacted poly pitch (CPP), which is challenging to scale further due to device parameters such as gate length, source/drain contact area, and gate spacer width.
Innovation Solution
A method for forming a field-effect transistor (FET) device with a novel design, involving the formation of a fin structure with alternating channel and non-channel layers, and subsequent lateral etching to create source, drain, and gate cavities, allowing for the formation of source/drain and gate bodies with a laterally offset configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET architecture with spacers is used, then gate and source/drain are electrically separated, but CPP (contacted poly pitch) cannot be scaled below approximately 50 nm due to minimum spacer length requirements
Solution Approach 1:
The patent transitions from a planar spacer-based separation approach to a three-dimensional offset configuration where the gate body is positioned at a lateral offset from the source/drain bodies. This dimensional change eliminates the need for spacers while maintaining electrical separation through the offset geometry, enabling CPP scaling below 50 nm.
Solution Approach 2:
The patent removes the spacer component entirely from the device architecture. By extracting the spacer and replacing it with an offset-based separation mechanism, the invention eliminates the minimum length constraint that previously limited CPP scaling.
2Length of moving object
If lateral offset configuration is implemented, then CPP scaling is enabled, but manufacturing complexity increases due to multi-side masking and selective etching processes
Solution Approach 1:
The patent forms the gate body and source/drain bodies in a specific sequence with preliminary masking steps. The gate body is formed first with masking on the first side, then source/drain bodies are formed with masking on the second side. This preliminary action approach organizes the complex multi-side masking process into manageable sequential steps.
Solution Approach 2:
The patent divides the fin structure into multiple parts (first fin part, second fin part, third fin part) and processes each part separately with selective masking. This segmentation of the fabrication process allows complex offset structures to be built through simpler, repeated operations on discrete segments.
3Length of moving object
If common gate body and common source/drain bodies are formed with lateral offset, then electrical separation is achieved without spacers, but precise positioning control is required
Solution Approach 1:
The patent employs asymmetric masking configurations where masking is applied on the first side during gate body formation and on the second side during source/drain body formation. This asymmetric approach enables precise lateral offset positioning by controlling which sides are exposed to etching at each fabrication stage.
Solution Approach 2:
By moving from co-planar to laterally offset positioning in the horizontal plane, the patent achieves precise spatial separation. The offset configuration in the lateral dimension provides inherent positioning control that prevents overlap while maintaining compact vertical stacking.
Data Source
Figure 1~2
Figure 3
Figure 4a~4b
AI summary
According to an aspect there is provided a method for forming a FET device, comprising: forming a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers; etching each of first and second fin parts from each of first and second opposite sides of the fin structure such that a set of source cavities extending through the first fin part is formed in a first set of layers of the layer stack, and such that a set of drain cavities extending through the second fin part is formed in the first set of layers of the layer stack; filling the source and drain cavities with a dummy material; while masking the fin structure from the second side: - removing the dummy material by etching from the first side, and - subsequently, forming a source body and a drain body, each comprising a respective common body portion and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively; and while masking the fin structure from the first side: - etching a third fin part from the second side such that a set of gate cavities extending through the third fin part is formed in a second set of layers, and - subsequently, forming a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion into the gate cavities.